Lead Emulation Engineer

Asteralabs; Bengaluru; On-site; INR 4,000,000 - 6,000,000; Full time

Job summary

Astera Labs in Bengaluru is seeking a Lead Emulation Engineer to drive the deployment and execution of complex SoC/IP verification on hardware emulation platforms. You will collaborate with DV, RTL, firmware, and architecture teams to accelerate verification, software development, and system-level validation.

The role requires leading emulation strategies, building scalable environments, and mentoring other engineers to optimize performance and efficiency across projects.

Qualifications

• Experience with ASIC/SoC emulation on hardware platforms.
• Strong RTL and digital design understanding.
• Proficient in SystemVerilog/Verilog and UVM-based verification.
• Experience with emulation compile, mapping, partitioning and acceleration.
• Scripting/programming in Python/Tcl/Perl/C/C++.

Responsibilities

• Lead emulation strategy and execution for complex SoC/IP designs.
• Develop and maintain emulation environments for large-scale ASIC/SoC designs.
• Bring up RTL on emulation platforms and debug issues.
• Develop and execute emulation-based verification plans.
• Enable software/firmware teams on emulated workloads.
• Support early software bring-up and system-level validation.
• Develop transactors, monitors, BFMs and other emulation components.
• Optimize emulation builds for performance and efficiency.
• Debug issues across RTL, testbench, and emulation environment.
• Collaborate with DV teams to migrate tests to emulation.
• Create automation for test execution and data collection.
• Analyze failures and drive root-cause with RTL/DV teams.
• Support performance benchmarking and system-level workload validation.
• Mentor engineers and drive emulation methodology improvements.

Skills

ASIC/SoC emulation

RTL design

SystemVerilog/Verilog

UVM verification

Scripting languages (Python/Tcl/Perl/C

Education

B.E./B.Tech/M.E./M.Tech in Electronics or related discipline

Tools

Cadence Palladium

Synopsys ZeBu

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Lead Emulation Engineer

Experience - 6–10years

Job Summary

We are looking for a Lead Emulation Engineer to lead the deployment and execution of complex SoC/IP verification on hardware emulation platforms. The candidate will work closely with design verification, RTL, architecture, firmware, and post-silicon teams to accelerate functional verification, software development, performance validation, and system-level debug.

Key Responsibilities

• Lead emulation strategy and execution for complex SoC/IP designs.
• Develop and maintain emulation environments for large-scale ASIC/SoC designs.
• Bring up RTL designs on emulation platforms and debug compilation, mapping, and runtime issues.
• Develop and execute emulation-based verification plans.
• Enable software and firmware teams to execute workloads on emulated hardware.
• Support early software bring-up and system-level validation.
• Develop transactors, monitors, BFMs, and other emulation components asrequired.
• Optimizeemulation builds for performance, capacity, and compile/runtime efficiency.
• Debug functional issues across RTL, testbench, emulation environment, and software.
• Work closely with DV teams to migrate suitable simulation-based tests to emulation.
• Develop automation for test execution, regression, data collection, and debug.
• Analyze emulation failures and drive root-cause identification with RTL/DV teams.
• Support performance and stress testing using realistic system workloads.
• Drive emulationmethodologyimprovements and infrastructure enhancements.
• Mentor junior and senior emulation engineers.
• Provide technical leadership during major IP/SoCbring-upmilestones.
• Support silicon bring-up by developing reusable emulation-based debug strategies.

Required Technical Skills

• Strong experience with ASIC/SoC emulation.
• Hands-on experience with platforms such as Cadence Palladium, SynopsysZeBu, or equivalent.
• Strong understanding of RTL and digital design.
• Experience with SystemVerilog/Verilog.
• Experience with UVM-based verification environments and simulation-to-emulation flows.
• Strong understanding of emulation compile, mapping, partitioning, acceleration, and runtime concepts.
• Strong debugging and problem-solving skills.
• Scripting/programming experience using Python,Tcl, Perl, or C/C++.

Preferred Experience

• Experience with large, complex SoCs and multi-IP environments.
• Experience with PCIe,UALink, CXL, Ethernet, NoC, memory systems, or other high-speed interfaces.
• Experience with software-driven validation and early firmware enablement.
• Experience developing custom transactors and acceleration models.
• Experience with performance benchmarking and system-level workload validation.
• Experience supporting pre-silicon and post-silicon debug.

Leadership Expectations

• Independently own emulation bring-up and execution for major IPs/subsystems.
• Lead technical discussions with DV, RTL, firmware, and architecture teams.
• Mentor engineers and improve emulation productivity.

Drive issues to closure while working against aggressive project/tape-out schedules.

Establish reusable emulation flows and best practices.

Education

B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Computer Engineering, VLSI, or a related discipline.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.