Lead Analog & Mixed-Signal (AMS) Circuit Designer

Qailash Labs; NTR; Hybride; INR 3 500 000 - 7 000 000; Plein temps

Résumé du poste

Qailash Labs in Vijayawada, India, seeks a Senior AMS Circuit Designer to lead transistor-level analog blocks from schematic sizing through post-layout verification. Hybrid work with flexible arrangements.

Candidates will design CTIA, SAR ADCs, bandgap references, and LDOs, perform Monte Carlo analyses, and collaborate with silicon architects and layout engineers to ensure robust, tape-out-worthy silicon.

Qualifications

• 4+ years of hands-on transistor-level custom analog circuit design with at least one taped-out IC
• Proficiency in Cadence Virtuoso/Spectre for schematic/analog design
• Strong knowledge of SPICE, Monte Carlo, and PSS/Pnoise analyses
• Experience with post-layout sign-off (PEX) and layout collaboration

Responsabilités

• Lead transistor-level schematic design, sizing, and verification for AMS blocks
• Design CTIA/DI/ CDS noise-filtering stages with ultra-low noise performance
• Develop high-resolution column-parallel SAR ADCs and DAC-related blocks
• Design curvature-compensated bandgap references and low-noise LDO regulators
• Perform multi-corner SPICE simulations across PVT with temperature effects
• Collaborate with Silicon Architects and Layout Engineers for SDL-driven layout and sign-off
• Create Verilog-A / SystemVerilog-AMS models for co-simulation

Connaissances

Transistor-level analog circuit design

SPICE simulation

AMS verification

Monte Carlo analysis

Noise modeling

Formation

M.Tech in Microelectronics

Ph.D. in Electrical Engineering (Analog & Mixed-Signal)

Outils

Cadence Virtuoso

Spectre / Spectre-AMS

ADE-XL / Assembler

Calibre PEX

Description du poste

Role Level: Core Engineering (Senior AMS Circuit Designer / Analog Lead)

Location: Vijayawada (AP) / Hybrid (Flexible)

Experience: 4+ years of dedicated hands-on experience in Transistor-Level Custom AMS Circuit Design with proven tape-out closure (or graduating M.Tech/Ph.D. with relevant silicon converter/front-end research)

APPLICANT SCOPE & SCREENING NOTICE (PLEASE READ CAREFULLY):

Strictly Custom Silicon IC Design: This position requires transistor-level schematic design, device sizing, and SPICE simulation of custom analog blocks in Cadence Virtuoso / Spectre.

Non-Applicable Profiles: Candidates whose experience is limited to standard cell library characterization (.lib modeling), automated digital RTL/FPGA implementation, or board-level (PCB) circuit design are not suitable for this silicon IC design role.

Role Overview:

Lead custom transistor-level schematic design, precision sizing, compact SPICE model verification, and AMS simulation of low-noise sensor front-ends, high-resolution column data converters, and precision power/bias management circuits on advanced deep-submicron CMOS and SOI process nodes. Working in close collaboration with our Silicon Architects and Custom Layout Engineers, you will own critical mixed-signal blocks from architectural definition through schematic sizing, Monte Carlo verification, and post-layout parasitic extraction (PEX) sign-off.

Key Responsibilities:

Sensor Front-End Design: Architect, size, and simulate low-noise Capacitive Transimpedance Amplifiers (CTIA), Direct Injection (DI), Buffered Direct Injection (BDI), and Correlated Double Sampling (CDS) noise-filtering stages to achieve ultra-low input-referred noise and wide dynamic range.

Column-Parallel Data Converters: Design high-resolution (12-bit to 14-bit), low-power column-parallel SAR ADCs operating within tight column-pitch constraints; implement asynchronous SAR timing control logic, monotonic/split-capacitor CDAC switching topologies, and dynamic comparators with Dynamic Offset Cancellation (DOC).

Precision References & Power Management: Design curvature-compensated bandgap voltage references, low-noise bias current distribution networks, and high-PSRR on-chip Low Dropout (LDO) regulators with stable operation under wide capacitive loading.

Extreme Temperature & PVT Verification: Perform rigorous multi-corner SPICE simulations across PVT corners (SS, FF, TT) and wide operational temperature envelopes, accounting for device threshold voltage shifts, carrier mobility variations, and leakage behavior.

Statistical & Noise Modeling: Execute comprehensive Monte Carlo mismatch simulations, transient noise analyses, and Periodic Steady-State (PSS / Pnoise) regressions to ensure robust yield and offset cancellation.

Layout Collaboration & Post-Layout Sign-Off: Collaborate directly with Custom Layout Engineers on schematic-driven layout (SDL), common-centroid matching, sensitive charge node shielding, and parasitic extraction (PEX) re-simulation to ensure zero post-layout performance degradation.

Behavioral Modeling: Develop Verilog-A and SystemVerilog-AMS behavioral models for full-chip mixed-signal co-simulation and automated digital top-level verification.

Qualifications & Technical Skills:

Education: M.Tech or Ph.D. in Microelectronics, VLSI Design, or Electrical Engineering with a focus on Analog & Mixed-Signal IC design.

Experience: 4+ years of hands-on transistor-level custom analog circuit design experience with at least one successfully taped-out IC (commercial or multi-project wafer shuttle).

Core Design Expertise: Proven track record in designing at least two of the following: SAR ADCs, CTIA / low-noise charge amplifiers, high-speed dynamic comparators, bandgap references, or on-chip LDO regulators.

EDA Tools Mastery: Deep proficiency in Cadence Virtuoso Schematic Editor, Spectre / Spectre-AMS, ADE-XL/Assembler, and post-layout extraction flows (Quantus / Calibre PEX).

Physics & Modeling Insight: Solid grasp of deep-submicron device physics, compact modeling (cryogenic-grade advanced-node compact device models, PSP), noise mechanisms (1/f and thermal noise), and device mismatch mitigation.

Professional Background: Prior experience at fabless semiconductor companies, analog IDMs, or specialized custom IC design houses is preferred.