[India] Senior UCIe Verification Engineer

EdgeCortix; Hyderabad; On-site; INR 2,600,000 - 4,500,000; Full time

Benefits offered by this job

Highly competitive salary and stock –-

Flex work time

Top-tier employee benefits

Job summary

Edgecortix is seeking a Senior UCIe Verification Engineer in Hyderabad to lead verification for UCIe IP, subsystems, and SoC integrations. You will develop reusable SystemVerilog/UVM environments, create constrained-random tests, and verify protocol features across a range of interfaces.

You will collaborate with architecture, RTL, firmware and validation teams, drive verification closure, and contribute to silicon bring-up activities.

Qualifications

• 6–12 years of functional verification using SystemVerilog and UVM.
• Hands-on verification of UCIe IP and chiplet interconnects.
• Experience with 1–2 successful SoC tape-outs and subsystems integration.

Responsibilities

• Develop and execute verification plans for UCIe IP, subsystems, and SoC integration.
• Build reusable SystemVerilog/UVM verification environments from scratch.
• Create constrained-random and directed test scenarios for UCIe functionality and protocol compliance.
• Verify UCIe protocol features: link training, sideband, adapter layer, protocol layer, data transfer, flow control, power management, error handling, and reset sequences.
• Ensure interoperability with PCIe, CXL, or streaming interfaces.
• Develop UVM agents, scoreboards, monitors, checkers, and coverage models.
• Write and debug SystemVerilog Assertions for protocol checks.
• Perform coverage analysis and drive functional and code coverage closure.
• Debug RTL and testbench; support gate-level simulations and silicon bring-up.
• Collaborate with architecture, RTL, DFT, firmware, physical design, and validation teams.

Skills

SystemVerilog

UVM

UCIe verification

SoC/subsystem verification

Constrained-random testing

Coverage-driven verification

SystemVerilog Assertions

RTL debugging

CI/CD tooling

Python scripting

Chiplet interconnects

Tools

SVA

Job description

Introduction

We are looking for a Senior UCIe Verification Engineer with strong experience in SystemVerilog/UVM-based verification of high-speed interconnects and SoC subsystems. The ideal candidate should have hands‑on experience in verifying UCIe (Universal Chiplet Interconnect Express) IP and should have contributed to at least 1-2 successful SoC tape‑outs. The role involves developing reusable verification environments, protocol compliance verification, subsystem/SoC integration, and driving verification closure.

About Edgecortix

At Edgecortix we are a deep-tech startup revolutionizing edge computing with artificial intelligence and novel high efficiency silicon on chip design. Originating from multiple years of research, our unique AI hardware & software co‑design principle and the Dynamic Neural Accelerator ® AI processor IP are geared towards positively disrupting the rapidly growing artificial intelligence edge hardware space and bring the power of AI and machine learning to all kinds of devices. Our operations are headquartered in Tokyo, Japan, with offices in Singapore, Virginia, California in the US. In addition, we are starting a new Design Center in India, located in Hyderabad.

The Team

As an engineering driven company we are working to define and solve the hardest problems in AI including computer vision, speech, and natural language, geared towards real‑time capabilities on small to medium form factor devices. We originated out of multiple years of research, as such at our core we value learning, intellectual curiosity, and self‑starters. We have the ambitious goal of enabling cloud‑level performance with significantly better energy‑efficiency for AI inference at the edge.

Your Role and Responsibilities

• Develop and execute comprehensive verification plans for UCIe IP, subsystems, and SoC integration.
• Build reusable SystemVerilog/UVM verification environments from scratch.
• Develop constrained‑random and directed test scenarios to verify UCIe functionality and protocol compliance.
• Verify UCIe protocol features, including:
  • Link initialization and training
  • Sideband communication
  • Adapter layer
  • Protocol layer
  • Data transfer and flow control
  • Link power management
  • Error detection and recovery
  • Reset and initialization sequences
• Verify interoperability between UCIe and upper‑layer protocols such as PCIe, CXL, or streaming interfaces.
• Develop UVM agents, scoreboards, monitors, protocol checkers, and functional coverage models.
• Write and debug SystemVerilog Assertions (SVA) for protocol compliance and interface checks.
• Perform coverage analysis and drive functional and code coverage closure.
• Debug RTL, protocol, and testbench issues using simulation and waveform analysis.
• Support gate‑level simulations, regression execution, and silicon bring‑up activities.
• Collaborate closely with architecture, RTL, DFT, firmware, physical design, and validation teams throughout the product development cycle.

Desired Qualifications

• 6-12 years of experience in functional verification using SystemVerilog and UVM.
• Strong experience in developing complete UVM verification environments from scratch.
• Good understanding of UCIe architecture and protocol.
• Experience verifying high-speed serial interfaces or chiplet interconnects.
• Strong understanding of:
  • AXI4
  • High‑speed protocol verification
  • Clock domain crossings (CDC)
  • Reset domain crossings (RDC)
  • Protocol compliance verification
• Experience with constrained‑random, assertion‑based, and coverage‑driven verification methodologies.
• Strong experience writing SystemVerilog Assertions (SVA).
• Experience with gate‑level simulation and timing‑aware verification.
• Excellent RTL and protocol debugging skills.
• Experience in verifying die‑to‑die interfaces or chiplet‑based architectures.
• Experience with subsystem and SoC‑level verification.
• Experience with emulator‑based verification platforms.
• Exposure to Formal Verification techniques.
• Familiarity with Continuous Integration (CI/CD) tools such as Jenkins or GitLab CI.
• Experience with scripting languages such as Python, Perl, or Tcl.
• Experience with version control systems such as Git.
• SoC Experience
  • Hands‑on experience in 1-2 successful SoC tape‑outs.
  • Experience integrating UCIe subsystems into complex SoCs.
  • Exposure to boot flows, clock/reset architecture, power management, and chiplet integration.
  • Experience collaborating with firmware and post‑silicon validation teams during bring‑up and debug.

What’s in it for you?

Make a difference: you will have the opportunity to join a well‑funded fabless AI semiconductor startup that is disrupting the AI software and hardware co‑design space. Be an integral part of its growth and momentum.

Benefits and Perks

• Highly competitive salary and stock options
• Flex work time
• Top‑tier employee benefits