Senior SoC Design Verification Engineer

Quadric; Maharashtra; On-site; INR 4,000,000 - 7,000,000; Full time

Benefits offered by this job

Medical insurance

Equity with the business

Paid Parental Leave

PF Retirement Plan

Flexible PTO

Winter holiday shutdown

Catered lunch

Downtown Pune office location

Collaborative culture

Innovative disruption

Job summary

Quadric seeks a Senior Design Verification Engineer to lead the development of its new SoC verification environment in Pune, India. You will architect scratch-built testbenches and drive verification coverage with cross-functional teams across HW and SW.

Strong UVM, SystemVerilog, and Python skills are essential. You will verify NoC, PCIe/UCIe, and DDR IP blocks, build scalable test plans, and establish robust co-simulation pipelines prior to tapeout.

Qualifications

• 5+ years of dedicated design verification experience on complex SoC/ASIC designs.
• Deep expertise in UVM methodology and leading SoC-level verification practices.
• Proficiency in SystemVerilog or Verilog, assembly programming, and scripting languages like Python.
• Hands-on experience verifying SoC subsystems and 3rd-party IP (e.g., NoC, PCIe/UCIe, DDR).
• Strong computer architecture background with experience in VCS and Verilog/C Co-Simulation.

Responsibilities

• Architect and build scratch-built testbenches for SoC-level verification.
• Collaborate with architects, HW designers, and SW teams to document verification plans.
• Develop directed and random drivers, stress-test subsystems, and verify 3rd-party IP blocks.

Skills

5+ years Verification

UVM methodology

SystemVerilog/Verilog

Python scripting

NoC/PCIe/DDR verification

Job description

About Quadric

Quadric is redefining edge AI with the industry's first General Purpose Neural Processing Unit (GPNPU), enabling developers to run both neural network inference and conventional C++ code on a single programmable architecture. Our technology powers intelligent edge devices across automotive, industrial, robotics, and embedded systems. Founded by technologists from MIT and Carnegie Mellon, Quadric is a well-funded growth-stage semiconductor IP company with a growing licensing business.

The Opportunity

Quadric is building a revolutionary new processor-based SoC architecture. As a Senior Design Verification Engineer, you will join the ground floor of our chip design team, taking technical leadership in architecting and building our SoC-level verification environment from scratch. You will collaborate closely with architects, hardware engineers, and software teams to ensure high quality and complete verification coverage for our next-generation GPNPU-based SoCs.

What You'll Do

Testbench Architecture & Test Plan Development

• Architect and build novel, scratch-built testbenches for SoC-level verification of our GPNPU-based SoCs.
• Collaborate cross-functionally with architects, HW designers, and SW teams to document comprehensive verification test plans.
• Implement scalable testbenches using commercial Verification IP (VIP) and/or internal software utilities.

Test Execution & Verification Coverage

• Develop directed and random drivers, as well as assembly or C++ programs, to efficiently stress-test SoC subsystems and integration.
• Verify complex SoC subsystems, including 3rd-party IP (e.g., NoC, PCIe/UCIe, DDR).
• Leverage VCS and Verilog/C Co-Simulation environments alongside assembly programming and Python scripting to execute test suites.
• Track, analyze, and communicate verification progress across teams using functional and code coverage metrics.

What Success Looks Like

Within your first 6-12 months, you'll:

• Build out and deploy a fully functional, scratch-built SoC-level UVM verification environment.
• Achieve target coverage metrics across all critical SoC subsystems and 3rd-party IP blocks.
• Establish robust co-simulation pipelines that validate HW/SW execution before tapeout.

What We’re Looking For

Required

• Minimum 5+ years of dedicated design verification experience on complex SoC/ASIC designs.
• Deep expertise in UVM methodology and leading SoC-level verification practices.
• Proficiency in SystemVerilog or Verilog, assembly programming, and scripting languages like Python.
• Hands-on experience verifying SoC subsystems and 3rd-party IP (e.g., NoC, PCIe/UCIe, DDR).
• Strong computer architecture background with experience in VCS and Verilog/C Co-Simulation.

What We Offer

In addition to a competitive salary, we offer a variety of benefits to support your needs. The benefits below reflect our India-based offerings; for roles in other locations, benefits vary and are shared during the hiring process. These include:

• Medical, dental, and vision insurance
• Equity with the business
• Paid Parental Leave
• PF Retirement Plan
• Flexible PTO
• Winter holiday shutdown
• Catered lunch each day in our office
• Downtown Pune office location, close to shops, cafes, and local amenities
• Collaborative, low-ego culture with significant ownership and impact
• A work culture focused on innovative disruption

Founded in 2016 and based in downtown Burlingame, California, Quadric is building the world’s first supercomputer designed for the real-time needs of edge devices. Quadric aims to empower developers in every industry with superpowers to create tomorrow’s technology, today. The company was co-founded by technologists from MIT and Carnegie Mellon, who were previously the technical co-founders of the Bitcoin computing company 21.

Quadric is proud to be an equal opportunity employer. We are committed to creating an inclusive environment where people from all backgrounds can do their best work. We consider all qualified applicants without regard to race, color, religion, sex, gender identity or expression, sexual orientation, national origin, age, disability, veteran status, or any other protected characteristic under applicable law.