[India] RTL Integration (Frontend) Engineer

EdgeCortix; Hyderabad; Sur place; INR 2 200 000 - 4 200 000; Plein temps

Avantages offerts par ce poste

Highly competitive salary

Flex work time

Top-tier employee benefits

Résumé du poste

EdgeCortix is seeking a Front-End Design Engineer for RTL integration to join our AI Hardware Team in Hyderabad. You will own IP integration into ASSP/SOC and help advance EdgeCortixDNA IP alongside third-party IPs, enabling next-generation edge AI hardware.

The ideal candidate has 4-7 years of RTL experience, strong Verilog, proficiency in C/C++, and familiarity with synthesis, STA, and power analysis. You’ll work across RTL design, verification, and physical design flows and participate in

Qualifications

• 4-7 years of RTL integration and front end design checks, STA, PPA.
• Knowledge of Chisel based environments.
• IP knowledge of PCIe/UCIe, AXI, DDR, NIC.
• RISC V integration experience is a plus.
• FPGA integration experience.
• Formal equivalence.

Responsabilités

• Own the IP integration into ASSP/SOC.
• Integrated EdgeCortix DNA IP and other third-party IP integration.
• Experience with RTL rule checkers (Lint), CDC, RDC, LEC.
• Solid proficiency with Verilog, C/C++ and other scripting languages (e.g. Tcl, Ruby, Perl, Python and Makefile).
• Experience in RTL design, Synthesis, Static Timing Analysis, RTL and Netlist Power Analysis.
• Good understanding of Gate level netlists and Physical design flows.
• Playing a key role in development of verification infrastructure, which would involve VIPs, different memory models, monitors, etc.
• ECO Flows, Elab checks, Physical Synthesis.
• Integration flow automation and improvements.
• Generating Design Constraints and Constraints Analysis.

Connaissances

RTL integration

Verilog

C/C++

Scripting

STA/Power

Gate-level nets

Physical design

IP integration

RISC-V

FPGA

Formal equivalence

Cadence tool chain

Outils

Cadence tool chain

VIPs

Description du poste

Introduction

We are seeking a highly motivated Front-End Design Engineer (RTL Integration) to join our Artificial Intelligence Hardware Team at EdgeCortix. In this role, you will take ownership of integrating our proprietary Dynamic Neural Accelerator® (DNA) IP and other third-party IPs into complex SoC architectures, contributing directly to the development of our next-generation AI hardware. This is an exciting opportunity to work at the forefront of AI–hardware co-design and help shape the future of high-performance, energy-efficient edge computing.

About EdgeCortix

At Edgecortix we are a deep-tech startup revolutionizing edge computing with artificial intelligence and novel high efficiency silicon on chip design. Originating from multiple years of research, our unique AI hardware & software co-design principle and the Dynamic Neural Accelerator ® AI processor IP are geared towards positively disrupting the rapidly growing artificial intelligence edge hardware space and bring the power of AI and machine learning to all kinds of devices. Our operations are headquartered in Tokyo, Japan, with offices in Singapore, Virginia, California in the US. In addition, we are starting a new Design Center in India, located in Hyderabad.

The Team

As an engineering driven company we are working to define and solve the hardest problems in AI including computer vision, speech, and natural language, geared towards real-time capabilities on small to medium form factor devices. We originated out of multiple years of research, as such at our core we value learning, intellectual curiosity, and self-starters. We have the ambitious goal of enabling cloud-level performance with significantly better energy-efficiency for AI inference at the edge.

Your Role and Responsibilities:

This role is part of the EdgeCortix Artificial Intelligence Hardware Team

• Own the IP integration into ASSP/SOC
• Integrated EdgeCortix DNA IP and other third-party IP integration
• Experience with RTL rule checkers (Lint), CDC, RDC, LEC
• Solid proficiency with Verilog, C/C++ and other scripting languages (e.g. Tcl, Ruby, Perl, Python and Makefile)
• Experience in RTL design, Synthesis, Static Timing Analysis, RTL and Netlist Power Analysis
• Good understanding of Gate level netlists and Physical design flows
• Playing a key role in development of verification infrastructure, which would involve VIPs, different memory models, monitors, etc.
• ECO Flows, Elab checks, Physical Synthesis
• Integration flow automation and improvements
• Generating Design Constraints and Constraints Analysis

Desired Qualifications:

• 4-7 years of relevant experience covering RTL integration and front end design checks, STA, PPA
• Knowledge of Chisel based environments
• IP knowledge of PCIe/UCIe, AXI, DDR, NIC
• RISC V integration experience is a plus
• FPGA integration experience
• Formal equivalence

Preferred Qualification:

• Cadence tool chain experience
• Prior CPU/Memory/Bus Integration at subsystem level.
• Good understanding of Physical design flows
• Strong Synthesis , Timing Analysis and Power Analysis experience
• Experience with scripting languages such as perl/python.

Looking for someone who is passionate to innovate and execute, a high-gear individual with multi-tasking capabilities, ready to solve challenging problems. Ideal candidate is a person who is personable, self-motivated and has excellent written and verbal communication skills.

What’s in it for you?

Make a difference: you will have the opportunity to join a well-funded fabless AI semiconductor startup that is disrupting the AI software and hardware co-design space. Be an integral part of its growth and momentum.

Location - Hyderabad

Benefits and Perks

• Highly competitive salary
• Flex work time
• Top-tier employee benefits