Immediate hiring for Physical Design Engineers for HYD Location

Modernize Chip Solutions (MCS); Hyderabad; On-site; INR 1,200,000 - 2,200,000; Full time

Job summary

Modernize Chip Solutions (MCS) invites experienced physical design engineers for Hyderabad location. Immediate hire with 4–8 years of experience in PD/PV, STA, and EMIR knowledge. The role focuses on low-power aware floor planning, placement, CTS, routing, RC extraction, and timing closure, with face-to-face interviews in Hyd.

Candidate should be proficient in DRC/LVS/ERC and tape-out activities, ready to contribute to 3 nm and 5 nm node projects in a fast-paced team.

Qualifications

• 4–8 years of hands-on experience in physical design (PD/PV) and STA.
• Strong experience in block-level low power aware floor planning, placement, CTS, routing, RC extraction, and timing closure.
• Proficiency in DRC/LVS/ERC and tape-out activities with EMIR knowledge.

Responsibilities

• Execute block-level physical design tasks: floorplanning, placement, CTS, routing and RC extraction to meet timing and area targets.
• Perform STA timing closure and EMIR analysis to ensure sign-off readiness.
• Collaborate on tape-out activities and maintain design-for-manufacturability standards.

Skills

Physical design

Low power aware design

Floor planning

Placement

Clock tree synthesis

Routing

RC extraction

STA timing closure

EMIR knowledge

DRC/LVS/ERC

Tape-out activities

Tools

Innovus

Tempus

Job description

We are immediate hiring for Physical design Engineers for HYD Location.

Exp - 4 to 8 yrs

Location - Hyd

Notice Period - immediate

Mode on interview - F2F only in Hyd location.

JD:

• Tool : Cadence flow ( Innovus & Tempus )
• Node : 3 nm & 5nm
• Strong exp in block level : PD/PV & STA with EMIR knowledge
• Should be proficient in block level low power aware floor planning, placement, clock tree synthesis, routing, RC extraction, STA timing closure, IR/EM analysis, DRC/LVS/ERC and tape out activities.