Head of Engineering

InterviewPanel; Bengaluru; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Level Five Cartronics, a fabless automotive semiconductor design company, seeks a hands-on Head of Engineering based in Bengaluru to lead the analog/mixed-signal design organization. You will drive PMICs, oscillators, PLLs and PCIe buffers across CMOS/BCD HV processes, from concept through tape-out and qualification.

You will build and mentor cross-functional teams, ensuring automotive reliability, jitter and EMC targets are met, and partner with product & test engineering to scale high-volume

Qualifications

• 12+ years in analog/mixed-signal design, layout and productization.
• Proven taped-out blocks and full-volume shipping experience.
• Deep knowledge of schematic, layout and lab characterization.
• Hands-on DC-DC and LDO design in CMOS/BCD HV processes.
• Expertise in clocking and low-noise PLLs and PCIe buffers.
• Experience with PMICs, oscillators and EMI suppression techniques.
• Strong familiarity with 55nm, 90nm and 180nm nodes.
• Extensive Cadence EDA usage across design/verification.
• Verilog/Verilog-AMS mixed-signal modeling.
• Track record of partnering with characterization and product teams.

Responsibilities

• Lead analog/mixed-signal design, layout and verification across multiple product lines.
• Own technical architecture for PMICs, oscillators, PLLs and PCIe buffers.
• Drive high-speed interfaces optimized for PCIe Gen 4–6 standards.
• Oversee design across 55/90/180 nm processes from spec to tape-out.
• Set design methodology and gates; review schematics and verification plans.
• Collaborate with characterization, product and test engineering.
• Work with product teams on productization, test development and yield.
• Build and scale cross-functional teams; recruit top talent in India.
• Be the technical authority for difficult design and silicon issues.

Skills

Analog/mixed-signal design

Layout

Verilog/Verilog-AMS

Cadence EDA

PMICs

Oscillators

PLL architectures

PCIe buffers

High-voltage processes 55/90/180 nm

Cross-functional leadership

Tools

Cadence tools

Job description

Do you want to own the PMIC, PLL, and PCIe buffer architectures that ship in millions of vehicles? Do you want to build and lead the team solving India's toughest automotive power and clocking challenges?

Role: Head of Engineering

Level Five Cartronics | Fabless Automotive Semiconductor Design

Location: MG Road, Bengaluru, Karnataka, India (On-site)

About Us

Founded by serial Entrepreneurs, Level Five Cartronics is a fabless semiconductor design company headquartered in Bengaluru, building automotive-grade Power Management ICs (PMICs), high-precision oscillators, and high-performance phase-locked loops (PLLs) for the next generation of vehicle electronics. Our portfolio centres on low-EMI power delivery including spread-spectrum EMI suppression and low-jitter clocking and interface solutions for safety-critical solutions and infotainment systems. We design DC-DC converters, LDOs, and clock distribution networks (including low-jitter PCIe Gen 4, 5, and 6 buffers) in CMOS and BCD high-voltage processes across the 55nm, 90nm and 180nm nodes. We own our products end to end, from architecture through silicon characterization and productization, as part of India's growing fabless semiconductor ecosystem.

The Role

We are looking for a hands-on Head of Engineering, based at our Bengaluru headquarters, to lead our analog/mixed-signal design organization. This is a senior leadership position for an engineer who has personally taken complex automotive power, clocking, and high-speed interface products from concept to high-volume production - and who can build, mentor, and scale the cross-functional team that does it again and again.

You will set the technical direction for our PMIC, oscillator, PLL, and PCIe buffer roadmaps, own design quality and tape-out readiness, and partner closely with characterization, product, and test engineering to ensure every product meets stringent automotive reliability, jitter, and EMC requirements.

What You’ll Do

• 1. Lead and grow the analog/mixed-signal design, layout, and verification teams across multiple product lines, based out of our Bengaluru engineering center.
• 2. Own the technical architecture and execution of automotive-grade PMICs, DC-DC converters, LDOs, low phase noise Fractional-N phase-locked loops (PLLs), and low-jitter PCIe Gen 4, 5, and 6 buffers.
• 3. Target high-speed interface applications by driving low phase noise PLL architectures explicitly optimized for PCIe Gen 4, 5, and 6 standards.
• 4. Drive designs across CMOS and BCD high-voltage processes at 55nm, 90nm and 180nm, from specification through tape-out and qualification.
• 5. Set and enforce design methodology, review gates, and tape-out criteria; review schematics, layout, and verification plans personally where it matters.
• 6. Partner with characterization engineers on lab bring-up, silicon debug, and correlation of measured results to simulation.
• 7. Work side by side with product engineers on productization, test development, yield, and sustaining.
• 8. Build and lead cross-functional teams; recruit, develop, and retain top analog and layout talent in India's semiconductor talent market.
• 9. Be a technical authority and final escalation point for difficult design and silicon issues.

What You’ll Bring

• Minimum of 12 years (preferably more) of experience in analog/mixed-signal design, layout, and productization.
• Demonstrated track record of taped-out databases and shipping full products in volume, not just isolated blocks.
• Deep expertise across the full flow: schematic design, layout, and lab characterization (understanding how each one constrains the others).
• Hands-on design of DC-DC converters and LDOs in CMOS and BCD high-voltage processes.
• Expertise in clocking and interfaces: deep understanding of low phase noise design, Fractional-N PLL architectures, and low-jitter PCIe Gen 4, 5, and 6 clock buffers/drivers.
• Experience with PMICs, oscillators, and spread-spectrum / EMI suppression techniques.
• Strong working knowledge of the 55nm, 90nm and 180nm process nodes.
• Extensive experience with Cadence EDA tools across the design and verification flow.
• Mixed-signal behavioral modeling in Verilog (Verilog/Verilog-AMS).
• Proven history of working closely with characterization and product engineers through bring