Chief / Lead Silicon Architect

Qailash Labs; NTR; On-site; INR 4,000,000 - 7,000,000; Full time

Benefits offered by this job

Equity ownership (ESOPs)

Job summary

Qailash Labs Private Limited in India seeks a Chief Silicon Architect / Senior Principal Consultant to lead silicon strategy, microarchitecture, PDK integration and multi-vendor tape-out sign-offs for advanced Analog/Mixed-Signal ICs and sensor interface SoCs.

You will define product roadmaps, guide transistor-level design, supervise SPICE audits, and serve as the technical authority for full-chip tape-outs while mentoring the engineering team across AMS, RTL, and physical design.

Qualifications

• Ph.D. or M.Tech in Electrical Engineering / Microelectronics / VLSI Design from a premier institute (or equivalent deep industry experience).
• 8+ years of hands-on experience in full-custom Analog/Mixed-Signal or SoC chip design with proven silicon tape-outs brought to successful fabrication.
• Deep mastery and sign-off authority in Siemens Calibre (DRC, LVS, PEX, DFM) and Cadence Virtuoso / .

Responsibilities

• Lead microarchitecture and full-custom implementation of monolithic mixed-signal ICs, specifying analog front-ends, high-speed data converters, precision bias circuits, and interfaces.
• Supervise foundry PDK setup, SPICE model verification and multi-corner sign-offs in Cadence/Spectre.
• Lead multi-vendor physical verification sign-off audits using Calibre, IC Validator, and Pegasus to guarantee tape-out readiness.
• Drive Power, Performance, and Area (PPA) optimization across analog and digital blocks.
• Architect silicon-level security locks (OTP provisioning and anti-tamper logic) to protect IP.

Skills

Executive leadership

AMS/SoC architecture

VLSI design

Tape-out execution

Education

Ph.D. in Electrical Engineering

Tools

Cadence Virtuoso

Siemens Calibre

Synopsys IC Validator

Job description

Company Description Qailash Labs Private Limited is a fast-growing fabless deep-tech semiconductor company designing next-generation, high-performance Analog & Mixed-Signal Integrated Circuits (AMS ICs), precision data converters, and custom sensor interface System-on-Chips (SoCs). We develop proprietary microelectronics architectures that push the limits of power, performance, and resolution across advanced CMOS and FD-SOI process nodes.

Our Mission & Technological Focus

We are dedicated to building world-class, proprietary semiconductor IP and custom ASICs. Our engineering team tackles demanding mixed-signal circuit challengesintegrating ultra-low-noise analog front-ends, high-speed column-parallel ADCs, on-chip precision voltage references, and digital timing logic into monolithic silicon solutions.

Our People Ethos - A Workplace of Care and Distinction

At Qailash Labs, our engineers are our most valued asset. We believe that pioneering world-class silicon requires an environment of deep care, psychological safety, and intellectual freedom. We foster a culture built on mutual trust, high ownership, and zero bureaucracy where every team member is empowered to do the best work of their career.

• Cutting-Edge Silicon Impact: Work on foundational mixed-signal silicon architectures, high-resolution data converters, and advanced custom ASICs.
• Deep Empathy & Care: Industry-leading employee wellness, flexible hybrid workflows, and an inclusive culture centered on trust and mutual respect.
• World-Class Mentorship: Collaborate directly with veteran semiconductor architects, distinguished research advisors, and senior VLSI leaders.
• Wealth Creation & Ownership: Generous equity ownership (ESOPs) ensuring every engineer shares directly in the long-term enterprise value we build.

Flexible engagement

• Flexible Engagement Models: We offer full-time leadership roles, executive advisory/consulting arrangements, and milestone-based project engagements to accommodate senior veterans and top specialists.
• Internship-to-Full-Time (PPO) Track: Structured 3-to-6-month research internships for graduating M.Tech / Ph.D. scholars with direct Pre-Placement Offers (PPOs) and accelerated equity vesting.
• Competitive Compensation & ESOPs: Highly competitive compensation packages, performance incentives, and meaningful founding stock options (ESOPs).
• State-of-the-Art EDA & Compute: Access to industry-leading Cadence, Siemens EDA (Calibre), and Synopsys tool suites on high-performance compute infrastructure.
• Hybrid & Flexible Work Culture: Trust-based work environment with hybrid/remote flexibility across major hubs (Vijayawada, Bengaluru, Hyderabad).

Role Overview

Role Level: Executive Leadership / Chief Silicon Architect (Full-Time or Senior Principal Consultant)Location: Vijayawada / Bengaluru / Hyderabad / Hybrid (Flexible)Experience: 8+ years in Advanced AMS/SoC IC Architecture & Tape-out Execution Role Description As Chief Silicon Architect, you will lead the complete silicon strategy, microarchitecture definition, PDK integration, and multi-vendor physical verification sign-off for complex custom Analog/Mixed-Signal ICs and sensor interface SoCs. You will define product roadmaps, lead transistor-level architecture, supervise SPICE simulation audits, and serve as the primary technical authority for full-chip tape-outs.

Key responsibilities

• Lead microarchitecture and full-custom implementation of monolithic mixed-signal ICs, specifying analog front-ends, high-speed data converters (high-resolution Column SAR ADCs), precision bias circuits, and digital timing interfaces.
• Supervise foundry PDK setup, SPICE model card verification (BSIM-IMG, BSIM4, PSP), and extreme multi-corner simulation sign-offs in Cadence Spectre / Spectre-X.
• Lead multi-vendor physical verification sign-off audits using Siemens Calibre (DRC, LVS, PEX, DFM), Synopsys IC Validator (ICV), and Cadence Pegasus to guarantee zero-defect GDSII tape-out readiness.
• Drive Power, Performance, and Area (PPA) optimization across all owned analog and digital silicon blocks.
• Architect silicon-level hardware security locks (including OTP key provisioning and anti-tamper logic) to protect core IP.
• Establish single-source specification automation workflows so architectural updates propagate automatically across schematics, register maps, testbenches, and drivers.
• Build, mentor, and direct the full engineering team across Analog AMS, Digital RTL, Systems Automation, and Physical Layout.

Qualifications and skills

• Ph.D. or M.Tech in Electrical Engineering / Microelectronics / VLSI Design from a premier institute (or equivalent deep industry experience).
• 8+ years of hands-on experience in full-custom Analog/Mixed-Signal or SoC chip design with proven silicon tape-outs brought to successful fabrication.
• Deep mastery and sign-off authority in Siemens Calibre (DRC, LVS, PEX, DFM) and Cadence Virtuoso / .