Graduate Engineer Trainee - VLSI or RTL Design

HC Robotics; Kolkata District; On-site; INR 300,000 - 450,000; Full time

Job summary

HC Robotics in Kolkata invites graduates for the Graduate Engineer Trainee (VLSI/RTL Design) role. Freshers or candidates with 0-3 years of hands-on RTL/VLSI training will fit the profile, with strong fundamentals in digital design and desire to work on ASIC/FPGA projects.

The role involves developing and debugging RTL designs using Verilog/SystemVerilog, running simulations, supporting FPGA prototyping, and assisting in synthesis and timing closure with the design team.

Qualifications

• B.E./B.Tech/M.Tech in ECE, EEE, EIE, VLSI & Microelectronics, or related disciplines
• VLSI/RTL Design training preferred
• Freshers or candidates with up to 3 years of experience welcome

Responsibilities

• Develop and debug RTL designs using Verilog/SystemVerilog
• Perform simulations to verify RTL blocks
• Support FPGA prototyping and integration
• Assist in synthesis and timing closure activities
• Collaborate with design and verification teams

Skills

Digital Electronics

RTL Design

Verilog/SystemVerilog

FSM Design

RTL Simulation

Education

B.E./B.Tech/M.Tech in ECE/EEE/EIE/VLSI & Microelectronics

Tools

Vivado

Git

Linux basics

Job description

Graduate Engineer Trainee VLSI / RTL Design

Location: Kolkata
Experience: 0 - 3 Years

Qualification:

• B.E./B.Tech/M.Tech in ECE, EEE, EIE, VLSI & Microelectronics, or related disciplines
• VLSI/RTL Design training preferred

Skills Required:

• Digital Electronics & RTL Design
• Verilog HDL, SystemVerilog Basics
• FSM Design, Combinational & Sequential Logic
• RTL Simulation & Debugging
• Basic FPGA Design Flow

Preferred Skills:

• ASIC Design Flow, Vivado
• STA & Synthesis Concepts
• UVM Fundamentals
• TCL Scripting, Linux, Git

Role: Develop and debug RTL designs using Verilog/SystemVerilog, perform simulations, support FPGA prototyping, assist in synthesis and timing closure activities, and collaborate with design and verification teams.

Ideal Candidate: Freshers or candidates with up to 3 years of experience, strong digital design fundamentals, hands-on RTL/VLSI training or projects, and a passion for ASIC/FPGA design.