FPGA Engineer — Module Firmware & Signal Processing

EMTensor GmbH; Bengaluru; On-site; INR 3,000,000 - 5,400,000; Full time

Job summary

EMTensor GmbH in Bengaluru is seeking an experienced FPGA Design Engineer to rebuild firmware for our imaging module. You own the RTL, testbench and bench validation, writing from a protocol specification and proving results on the bench end-to-end—from ADC pins through DSP to the bus frame.

This hands-on role requires strong Verilog/SystemVerilog or VHDL skills, timing discipline, fixed-point DSP, and fluency with Intel Quartus and Xilinx Vivado.

Qualifications

• 4+ years of production FPGA development - shipped hardware, not evaluation boards.
• Strong RTL design in Verilog, SystemVerilog or VHDL: FSMs, synchronous design, parameterised modules.
• Experience with Intel/Altera Quartus; willingness to work in the Intel toolchain and cross-vendor experience.
• Timing discipline: STA, SDC constraints, setup/hold, CDC, metastability.
• DSP in fixed point: FIR/IIR, CIC, FFT/DFT, Q formats, truncation, overflow and saturation.
• Board interfaces: ADC capture, LVDS, SPI, I2C, UART, multipoint buses.
• Memory/buses: SRAM, FIFOs, AXI-Lite, register maps.
• Verification: self-checking testbenches; match against Python/MATLAB model.
• Bench debugging: JTAG, logic analyzers, latency measurement.

Responsibilities

• Own RTL from specification to testbench and reference model.
• Write and validate testbenches and ensure end-to-end verification.
• Validate amplitude and phase against reference models on bench hardware.
• Collaborate to ship hardware and enable handover with reproducible builds.

Skills

FPGA development

Verilog/SystemVerilog/VHDL

RTL design

Timing analysis

DSP fixed point

Board interfaces

CIC/FFT/DFT

Verification

Tooling

Tools

Intel Quartus

Xilinx Vivado

ModelSim/QuestaSim/Verilator

Job description

The Role

We are rebuilding the firmware for the digital modules at the heart of our imaging system - a large array of identical FPGA-based boards that capture, process and report data in lock-step.

The work is a clean-room implementation: you build the design from a written protocol specification, and you validate it against a working reference system. This is not a maintenance role and it is not code archaeology - you write the RTL, you write the testbench, and you prove on the bench that the numbers come out right.

The device has no processor subsystem and no operating system. Everything happens in fabric, with a small soft core for housekeeping. If you enjoy owning a design end to end - from the ADC pins through the DSP chain to the bus frame that leaves the board - this is that job.

What You Will Build

Bus

Serial multipoint bus slave: 72-bit frame, reply shifted by one clock, CRC at line rate. Shared return line across 16 modules, output enabled only when granted.

Capture

Parallel ADC capture, 14-bit at 20 MSPS, with the sampling window proven - not assumed.

Processing

CIC decimation with a programmable rate, windowing, single-bin DFT. Fixed point throughout, with word growth under control.

Control

SPI master driving four devices with different word lengths, clock dividers and chip selects.

Boot

Configuration from external flash: two images with fallback, plus firmware update over the bus to 192 modules with integrity checking.

Verification

Reference model in Python (NumPy) or MATLAB; the RTL must match it in both amplitude and phase.

Required Qualifications

• 4+ years of production FPGA development - shipped hardware, not evaluation boards.
• Strong RTL design in Verilog, SystemVerilog or VHDL: finite state machines, synchronous design, parameterised modules, disciplined coding style.
• Intel/Altera Quartus (Prime or II). Deep Xilinx/Vivado experience is welcome, but you must be willing and able to work in the Intel toolchain - and be able to show you have moved between vendors before.
• Timing as a discipline: static timing analysis, SDC constraints, setup and hold, clock-domain crossing, synchronisers, metastability, on-chip PLLs and dividers.
• DSP in fixed point: FIR/IIR filters, decimation and interpolation, CIC, windowing, FFT/DFT, DDS/NCO, quadrature processing, Q format, truncation, rounding, overflow and saturation.
• Board-level interfaces: parallel ADC capture, source-synchronous sampling and phase alignment, LVDS and differential pairs, SPI, I²C, UART, multipoint buses.
• Memory and buses: external SRAM, FIFOs, dual-port memory, buffering, Avalon-MM or AXI-Lite, register maps.
• Verification you write yourself: self-checking testbenches in ModelSim, QuestaSim or Verilator, compared against a Python or MATLAB golden model.
• Bench debugging: SignalTap or ILA, logic analyser, oscilloscope, JTAG, latency measurement, and the patience to chase intermittent behaviour.
• Tooling that survives handover: TCL build scripts, git, reproducible builds, code review.

Preferred Qualifications

• Soft processor work: Nios II, MicroBlaze or RISC-V - bootloader, configuration flash, JTAG programming.
• Experience implementing a design from a specification where no source code was available, with a reference unit to measure against.
• Portability work: migrating between FPGA families or vendors, replacing IP cores, writing code free of vendor primitives.
• Background in radar, test and measurement, or scientific instrumentation.
• Firmware update and integrity-checking schemes across large numbers of identical nodes.

Not a Fit

• Entirely on microcontrollers rather than FPGA fabric.
• Entirely around a processor subsystem and Linux (Zynq PS, PetaLinux, driver work) - our device has neither.
• Integrating ready-made cores in a graphical block builder, with no RTL of your own.
• Verification only, with no design ownership.
• Academic or evaluation-board projects only.
• A list of technologies with no project you can describe in detail.

Why Join EMTensor

We are building a team of exceptional engineers to solve some of the hardest problems in signal processing, FPGA design and imaging.

At EMTensor you work in a small, highly technical team where every engineer has a meaningful impact on the product and on the company. We value technical excellence, ownership, curiosity, and the ability to solve difficult problems.

If you are passionate about building world-class technology and want to work alongside other top engineers on problems that truly matter, we would love to hear from you.

Also advertised as:

FPGA Design Engineer

• RTL Design Engineer
• Firmware Engineer (FPGA)