Firmware Developer

Wrtr Ink Llp; India; Remote; INR 1,500,000 - 2,300,000; Full time

Job summary

Wrtr Ink Llp is seeking an experienced embedded firmware engineer to drive bring-up and validation of complex ASIC/SoC accelerators. The role covers secure boot, clock/power domain management, and high-speed interfaces, including 400G Ethernet and RDMA offloads.

You will work closely with hardware and Linux driver teams to ensure systems are robust, traceable, and scalable for AI workloads in data-center environments.

Qualifications

• 5+ years embedded firmware (C/C++/Rust) on ASIC/SoC or GPU-like accelerators.
• Proven experience with PCIe bring-up (enumeration, BARs, MSI-X, DMA engines), memory subsystems (HBM/GDDR/DDR).
• Configuration and management of clock/power domains, and RAS features.
• Comfortable reading schematics, register specs, and debugging with JTAG/logic analyzers.
• Strong documentation and code review habits; your code will be foundation for others.

Responsibilities

• Boot and Security: implement secure boot chain, device identity, attestation, anti-rollback, and field updates.
• Hardware Bring-Up: initialize clocks, power, HBM, PCIe, NoC, and SerDes PHYs for first-time-right deployment.
• High-Speed Networking: bring up 400G Ethernet interfaces and coordinate with network stack for RDMA offload engines.
• Runtime Excellence: power/thermal control, DVFS, watchdogs, RAS, and error recovery for 99.99% uptime.
• Host Communication: design mailbox protocols, MSI/MSI-X, DMA coordination, and health reporting with Linux driver team.
• Telemetry & Observability: unified event tracing with synchronized timestamps.
• Multi-Die Scaling: discovery, link training, topology management, load-balancing hooks across chiplets.
• Validation & Documentation: bring-up guides, scripted tests, HAL/config schemas for global support.

Skills

Embedded firmware

C/C++/Rust

PCIe bring-up

Memory subsystems

JTAG/logic analyzers

Documentation habits

Systems thinking

Tools

JTAG

Logic analyzers

PCIe verification tooling

Job description

Role & responsibilities

• Boot & Security: Implement our secure boot chain (BootROM PBL/SBL RTOS), device identity, attestation, anti-rollback, and field updates that protect our customers' valuable AI models and data.


• Hardware Bring-Up: Initialize clocks, power, HBM, PCIe, NoC, and SerDes PHYs often before our silicon arrives (emulation/FPGA), ensuring first-time-right deployment.


• High-Speed Networking: Bring up 400G Ethernet interfaces, configure MAC/PCS/FEC layers, and coordinate with network stack for RDMA offload engines essential for distributed AI training.


• Runtime Excellence: Power/thermal control, DVFS, watchdogs, RAS (ECC, crash dumps), and error recovery that delivers the 99.99% uptime our datacenter customers demand.


• Host Communication: Design mailbox protocols, MSI/MSI-X, DMA coordination, and health reporting with our Linux driver team to enable seamless integration.


• Telemetry & Observability: Unified event tracing with synchronized timestamps (PTP/PHC) giving our customers unprecedented visibility into their AI infrastructure.


• Multi-Die Scaling: Discovery, link training, topology management, and load-balancing hooks across chiplets because AI models keep growing.


• Validation & Documentation: Own bring-up guides, scripted tests, HIL/emulation validation, and HAL/config schemas that enable our global support team and customers.

Preferred candidate profile

• 5+ years embedded firmware (C/C++/Rust) on ASIC/SoC or GPU-like accelerators


• Proven experience with one of the complex high-speed subsystems is a must: PCIe bring-up (enumeration, BARs, MSI-X, DMA engines), memory subsystems (HBM/GDDR/DDR), high-speed Ethernet 100G+


• Configuration and management of clock/power domains, and RAS features


• Comfortable reading schematics, register specs, and debugging with JTAG/logic analyzers


• Strong documentation and code review habits your code will be the foundation others build upon


• Systems thinking: understanding how firmware decisions impact the full stack from silicon to application