Firmware Architect

Mulya Technologies; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Mulya Technologies is hiring for a Principal / Senior Staff Embedded Firmware Engineer to lead high-speed SerDes firmware development in Bengaluru. You will architect 224G/lane retimer firmware, drive link training, FEC, and telemetry integration.

You will collaborate with ASIC design and signal integrity teams, ensure IEEE 802.3ck/dj and OIF-CEI conformity, and travel up to 15% for silicon bring-up and standards meetings.

Qualifications

• BS in EE/CE/CS; MS preferred with DSP/comms focus.
• 8–10 years embedded firmware in high-speed SerDes/retimer products.
• Silicon bring-up from first samples to production experience.
• IEEE 802.3ck/802.3dj link training and RTOS on constrained MCUs.

Responsibilities

• Define firmware architecture for 224G/lane AEC retimer (boot, config, calibration, link training, FEC, telemetry).
• Implement link training for IEEE 802.3ck and 802.3dj with adaptation algorithms.
• Own FEC interaction (KP4, RS-544) and telemetry pipeline for predictive telemetry.
• Lead silicon bring-up with ASIC design and signal integrity teams.
• Ensure compliance with IEEE 802.3ck/dj, OIF-CEI, CMIS, OSFP standards.
• Travel up to 15% for bring-up and standards meetings.

Skills

C/C99/MISRA

Assembly for critical paths

Python for tools

CI/CD & static analysis

RTOS (FreeRTOS/Zephyr)

SerDes fundamentals

Standards awareness (IEEE 802.3ck/dj,O

Education

BS in Electrical Engineering/Computer Engineering/Computer Science

MS preferred, DSP/comms focus

Tools

FreeRTOS

Zephyr

Job description

We are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

Our architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.

JOB DESCRIPTION:

Responsibilities:

• Define firmware architecture for 224G/lane AEC retimer (boot, config, calibration, link training, equalization, FEC, telemetry)
• Implement link training for IEEE 802.3ck (100G/lane) and 802.3dj (200G/lane), including adaptation algorithms and fallbacks
• Own FEC interaction (KP4, RS-544) and telemetry pipeline for Predictive Telemetry
• Lead silicon bring-up, partnering with ASIC design and signal integrity
• Ensure standards compliance (IEEE 802.3ck/dj, OIF-CEI, CMIS, OSFP)
• Travel: Up to 15% (silicon bring-up, standards meetings)

Skills:

• Good knowledge of C (C99, MISRA), assembly for critical paths, Python for tools
• Good knowledge of CI/CD, static analysis, hardware-in-loop tests
• Good understanding of standards implementation (IEEE 802.3, OIF)
• Good knowledge of SerDes architecture (equalization, telemetry, interrupts)
• Self-motivated, with strong sense of ownership and responsibility
• Good communication and reporting skills

Experience:

• Principal / Senior Staff (8-10 years post-degree)
• 8-10 years embedded firmware in high-speed SerDes/retimer products
• Silicon bring-up as lead (first samples to production)
• IEEE 802.3ck and 802.3dj link training experience
• RTOS (FreeRTOS/Zephyr) on constrained MCUs (1MB flash, 256KB RAM)

Education:

• BS in Electrical Engineering, Computer Engineering, or Computer Science (MS preferred, DSP/comms focus)