Staff Embedded Firmware Engineer — Platform Controller (Zephyr RTOS)

TylSemi, Inc.; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

TYLsemi, Inc. seeks a Staff Embedded Firmware Engineer for the Platform Controller. You will own Zephyr RTOS firmware from pre-silicon bring-up through production release, collaborating across design, DV, and systems teams.

You will design and maintain Zephyr-based firmware, implement device drivers, and contribute to CI, debugging, and documentation. A strong background in embedded systems and AI/ML for fault analysis is required.

Qualifications

• 8–10 years of professional embedded firmware development in C, with exposure to modern C++ or Rust.
• RTOS experience on 32-bit MCUs (Arm Cortex-M or RISCV).
• Strong grasp of serial protocols: I2C, SPI, UART, with timing considerations.

Responsibilities

• Design, implement, and maintain Zephyr RTOS firmware for platform management controller, including device drivers and subsystem integration.
• Write and upstream-quality-review drivers against Zephyr's model — devicetree bindings, Kconfig, init levels and priorities.
• Deploy and maintain lightweight ML inference on target for anomaly detection and predictive fault analysis.
• Perform post-silicon bring-up: first-boot debug, clock/reset validation, bus enumeration, RTL-vs-firmware triage.
• Debug using JTAG/SWD, ETM/ITM trace, protocol analyzers, logic analyzers for intermittent/multi-master issues.
• Build and extend CI: unit tests, Twister, hardware-in-the-loop regression, static analysis gates.
• Write documentation for design guides, bring-up notes, and release notes.

Skills

Embedded firmware

RTOS experience

Serial protocols I2C/SPI/UART

Debugging

GCC/Clang

Python scripting

CI systems

Applied AI/ML knowledge

Education

BS or MS in Electrical Engineering / Computer Engineering / Computer Science

Tools

Zephyr RTOS

JTAG/SWD debuggers

Git

GCC/Clang

CMake

Python

Twister

Job description

Staff Embedded Firmware Engineer — Platform Controller (Zephyr RTOS)

About this position

About TYLsemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TYLsemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why Now

The Market Window

The semiconductor industry is going through its biggest architectural shift in 40 years:

• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.
• Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We Work

No Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.
• No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

• US team: Bay Area preferred, but we hire the best people regardless of location
• India team: Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

What We Value

• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.
• Bias for action. We move fast. Analysis paralysis doesn't fly here.
• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
• Low ego, high standards. We don't care about titles or politics. We care about results.

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's why you should:

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.
• The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.
• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.
• The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.

READY TO JOIN?

Role Overview

We are building the firmware that runs on our platform management controller: a Zephyr -based system responsible for power sequencing, rail telemetry, board health, and secure boot on next-generation silicon. This Staff Embedded Firmware Engineer — Platform Controller (Zephyr RTOS) owns firmware from pre-silicon bring-up through production release, working shoulder-to-shoulder with design, DV, and systems teams.

What you’ll do

• Design, implement, and maintain Zephyr RTOS firmware for platform management controller, including device drivers, subsystem integration, and application-level services.
• Write and upstream-quality-review drivers against Zephyr's driver model — devicetree bindings, Kconfig, init levels and priorities, struct device APIs.
• Deploy and maintain lightweight ML inference on target for anomaly detection and predictive fault analysis; own the path from trained model to running firmware.
• Perform post-silicon bring-up: first-boot debug, clock and reset validation, bus enumeration, triage of RTL-versus-firmware ambiguity with design teams.
• Debug hard problems using JTAG/SWD, ETM/ITM trace, protocol analyzers, and logic analyzers — including intermittent, timing-dependent, and multi-master bus failures.
• Build and extend CI: unit tests, Twister test suites, hardware-in-the-loop regression, static analysis gates.
• Write the documentation your teammates and customers will actually rely on — design docs, bring-up guides, register-level notes, release notes.

Required qualifications

• 8–10 years of professional embedded firmware development in C, with meaningful exposure to modern C++ or Rust.
• Deep, hands-on RTOS experience on 32-bit microcontrollers (Arm Cortex-M or RISCV) — scheduling, priority assignment, ISR design, synchronization primitives, and the failure modes each one produces.
• Strong grasp of serial protocols at the wire level: I2C, SPI, UART — arbitration, clock stretching, timing parameters, and how they break.
• Practical debugging skill with JTAG/SWD debuggers, oscilloscopes, logic analyzers, and protocol decoders.
• Comfort with the toolchain: Git, GCC/Clang, CMake, Python scripting, and CI systems.
• Applied AI/ML knowledge — at minimum, a working understanding of model training and deployment workflows, quantization and its accuracy cost, inference latency and memory budgeting on constrained targets, and honest judgment about when ML is and is not the right tool for a control problem.
• BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.

Preferred qualifications

Strong candidates will have direct experience with several of the following. We do not expect all of them.

RTOS and platform

• Zephyr RTOS in production: devicetree, Kconfig, west workspaces, SYS_INIT and device init ordering, Twister, upstream contribution history.
• Bare-metal and boot-path firmware, including boot ROM code, secure boot chains, and ROM-to-application handoff.
• On-chip bus fabric familiarity — AMBA APB / AHB — and what a fabric-level stall or misconfigured bridge looks like from the firmware side.

Peripherals and subsystems

• PMBus and SMBus — command sets, PEC, ALERT handling, multi-master and bus-recovery behavior.
• QSPI flash: XIP, DMA-driven transfers, dual/quad modes, flash programming and update paths.
• GPIO expanders and pin multiplexing; PWM and PIT/timer peripherals for control loops and precise sequencing.
• Watchdog design — windowed watchdogs, task-level petting strategies, and failure-mode analysis.
• Interrupt controller configuration nested and prioritized interrupts, latency measurement and reduction.
• Telemetry subsystem design: ADC sampling strategy, calibration, scaling, and out-of-band reporting.
• Debug and trace infrastructure — ETM/ITM, SWO, coresight, trace-based performance and timing analysis.
• AI based coding experience is must