Firmware Architect

Mulya Technologies; Hyderabad; In loco; INR 6.000.000 - 9.500.000; Tempo pieno

Descrizione del lavoro

Kandou Technologies in Hyderabad seeks a Principal / Senior Staff embedded firmware engineer to define firmware architecture for high-speed SerDes and AI memory fabric. You will lead silicon bring-up, collaborate with ASIC design and signal integrity, and drive standards compliance for cutting-edge hardware.

Responsibilities include implementing link training for 100G and 200G lanes, owning FEC and telemetry pipelines, and coordinating with cross-functional teams.

Competenze

• 8–10 years embedded firmware in high-speed SerDes/retimer products.
• RTOS (FreeRTOS/Zephyr) on constrained MCUs.
• Silicon bring-up as lead and experience with standards.

Mansioni

• Define firmware architecture for 224G/lane AEC retimer (boot, config, calibration, link training, equalization, FEC, telemetry).
• Implement link training for IEEE 802.3ck (100G/lane) and 802.3dj (200G/lane), including adaptation algorithms and fallbacks.
• Own FEC interaction (KP4, RS-544) and telemetry pipeline for Predictive Telemetry.
• Lead silicon bring-up, partnering with ASIC design and signal integrity.
• Ensure standards compliance (IEEE 802.3ck/dj, OIF-CEI, CMIS, OSFP).
• Travel: Up to 15% (silicon bring-up, standards meetings).

Conoscenze

C

Assembly

Python

CI/CD

Static Analysis

Hardware-in-loop

IEEE 802.3

SerDes

Ownership

Communication

Formazione

BS in Electrical Engineering

BS in Computer Engineering

BS in Computer Science

MS in DSP/Communications (preferred)

Strumenti

FreeRTOS

Zephyr

Descrizione del lavoro

We are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

Our architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.

JOB DESCRIPTION:

Responsibilities:

• Define firmware architecture for 224G/lane AEC retimer (boot, config, calibration, link training, equalization, FEC, telemetry)
• Implement link training for IEEE 802.3ck (100G/lane) and 802.3dj (200G/lane), including adaptation algorithms and fallbacks
• Own FEC interaction (KP4, RS-544) and telemetry pipeline for Predictive Telemetry
• Lead silicon bring‑up, partnering with ASIC design and signal integrity
• Ensure standards compliance (IEEE 802.3ck/dj, OIF-CEI, CMIS, OSFP)
• Travel: Up to 15% (silicon bring‑up, standards meetings)

Skills:

• Good knowledge of C (C99, MISRA), assembly for critical paths, Python for tools
• Good knowledge of CI/CD, static analysis, hardware‑in‑loop tests
• Good understanding of standards implementation (IEEE 802.3, OIF)
• Good knowledge of SerDes architecture (equalization, telemetry, interrupts)
• Self‑motivated, with strong sense of ownership and responsibility
• Good communication and reporting skills

Experience:

• Principal / Senior Staff (8-10 years post‑degree)
• 8-10 years embedded firmware in high-speed SerDes/retimer products
• Silicon bring‑up as lead (first samples to production)
• IEEE 802.3ck and 802.3dj link training experience
• RTOS (FreeRTOS/Zephyr) on constrained MCUs (1MB flash, 256KB RAM)

Education:

• BS in Electrical Engineering, Computer Engineering, or Computer Science (MS preferred, DSP/comms focus)

If this is the role you have been looking for and you want to be part of a growing Company, with an exciting future then we would really love to hear from you. Together We Kandou It!