DSP Architect

Mulya Technologies; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Mulya Technologies in Bengaluru, India, is seeking an experienced DSP Architect to lead SerDes DSP algorithm development for high-speed links (Ethernet/PCIe/UCIe) and pre-silicon validation.

The ideal candidate has 10+ years in DSP for SerDes PHYs, strong RTL/FPGA prototyping, and hands-on lab experience with high-speed test equipment. You will collaborate across hardware and IP teams to enable robust SoCs.

Qualifications

• 10+ years in DSP algorithm development for SerDes PHYs.
• Experience with high-speed serial links (Ethernet, PCIe, UCIe).
• Strong RTL design and FPGA prototyping experience.
• Proficiency with Cadence tools for synthesis and formal verification.

Responsibilities

• Develop and optimize DSP algorithms for SerDes PHYs (Ethernet/PCIe/UCIe).
• Prototype DSP blocks on FPGA platforms for pre-silicon validation.
• Perform lab debug and silicon characterization of high-speed links.
• Collaborate with analog/mixed-signal teams on CDR, PLL/DLL, equalization schemes.
• Document workflows and support IP integration into customer SoCs.

Skills

DSP algorithms

SerDes PHYs

FPGA prototyping

Cadence tools

Education

B.E./M.Tech in Electrical/Electronics Engineering (Signal processing)

Tools

MATLAB

Python

Cadence Genus

Innovus

JasperGold

Vivado

Quartus

Job description

We are a leading provider of high-performance, ultra-low power IP cores optimized for advanced semiconductor nodes, enabling the development of cutting-edge systems-on-chip (SoCs) for applications such as 5G, AI, LiDAR, radar, networking, and IoT. Known for its innovative small geometry solutions, our expertise encompasses data converter IP cores ranging from 6-bit to 14-bit resolutions and sampling rates up to over 20 Gsps.

Apart from the above we need 10+ year DSP engineers with Serdes background.

DSP Architect (10+ Years)

Core Expertise

• DSP Algorithms for SerDes:
• Deep knowledge of equalization (FFE/DFE), echo cancellation, adaptive filtering, CDR loops.
• Experience across Ethernet, PCIe, UCIe high-speed serial links.
• Skilled in channel modelling, jitter/noise analysis, BER optimization.
• Digital RTL & FPGA Prototyping:
• Strong background in RTL design and verification using Cadence digital tools (Knowledge wrt Genus for synthesis, Innovus for P&R, JasperGold for formal verification).
• Hands-on FPGA prototyping of SerDes DSP blocks (Xilinx Vivado, Intel Quartus).
• Implemented training sequence debug, retimer logic, and sideband channel handling on FPGA platforms.
• Bench expertise with oscilloscopes, BERTs and high-speed probes.
• Experience in silicon bring-up, validation, and correlation with simulation models.

Qualifications

• Education: B.E./M.Tech in Electrical/Electronics Engineering (Signal processing specialization).
• Experience: 10+ years in DSP algorithm development for SerDes PHYs.
• Tools & Languages:
• MATLAB, Python (algorithm modeling, post-processing).
• FPGA toolchains.
• Soft Skills: Analytical problem-solving, cross-functional collaboration, clear technical communication.

Responsibilities

• Develop and optimize DSP algorithms for SerDes PHYs (Ethernet/PCIe/UCIe).
• Prototype DSP blocks on FPGA platforms for pre-silicon validation.
• Perform lab debug and silicon characterization of high-speed links.
• Collaborate with analog/mixed-signal teams on CDR, PLL/DLL, equalization schemes.
• Document workflows and support IP integration into customer SoCs.