SERDES AMS Design Engineer

Ceremorphic, Inc.; Hyderabad; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Ceremorphic, Inc. in Hyderabad is seeking a SERDES Senior/Staff Designer to lead the design of critical components in high-speed PHY systems such as PCIe and USB. The ideal candidate will have strong skills in analog/mixed-signal design, circuit trade-off analysis, and hands-on experience in FinFet technology.

Responsibilities include ensuring successful tape-out and silicon validation while effectively communicating technical specifications. This role presents an exciting opportunity to work at the forefront of AI hardware development.

Qualifications

• Strong understanding of analog/mixed-signal design theories and practical concepts.
• Experience in circuit trade-off analysis and system-level specs comprehension.
• Proven track record in successful tape-out and silicon characterization.

Responsibilities

• Design core components of the high-speed PHY including PCIe, Ethernet, and USB.
• Perform critical layouts and ensure specifications are met.
• Communicate technical issues and conduct technical reviews.

Skills

Analog/mixed-signal design

High-speed PHY components knowledge

Circuit trade-off analysis

Critical layouts in FinFet

Technical communication

Job description

Ceremorphic AI hardware combines knowledge across many domains, including AI, compilers, computer architecture, analog circuits, and memories.

A key component of our system is the high-speed interconnect. The SERDES Senior/Staff Designer would be in charge of a core part of the high-speed PHY, including PCIe, Ethernet, and USB, in advanced FinFet technology nodes. A strong understanding of analog/mixed-signal circuit theories, and expert hands‑on design skills, are keys to a successful candidate for this position.

Key Requirements

• Strong understanding of analog/mixed-signal design theories and practical concepts such as mismatch, ratio-metric, linearity, stability, noise, and low‑power
• Strong understanding of one of the following core components of a high-speed PHY: CDR, PLL, PI, CTLE, TX Driver, Serializer/De-Serializer
• Experience in circuit trade‑off analysis and ability to comprehend system‑level specs and their impacts on circuit design, knowledge of PAM4 systems is a plus.
• Understanding of the physical layout requirements and hands‑on ability to perform critical layouts, experience in FinFet a plus
• Proven track record of successful tape‑out and silicon meeting performance and power specifications, and experience in chip debug/validation/characterization.
• The ability to communicate technical issues and present technical reviews coherently and logically are essential.