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Capgemini Engineering in Bengaluru seeks a Senior Verification Engineer to define and lead verification strategy for complex SoCs and subsystems, ensuring closure from specification to tapeout through scalable methodologies.
The role requires 12+ years of DV experience, expertise in UVM/SystemVerilog/Assertions, and hands-on work with emulation platforms; familiarity with PCIe/DDR/Ethernet/UCIe is a plus. Remote-friendly, with flexible schedules and global collaboration.
Define and lead verification strategy for complex SoCs and subsystems, ensuring verification closure from specification through tapeout using scalable methodologies.
Define and lead verification strategy for complex SoCs and subsystems, ensuring verification closure from specification through tapeout using scalable methodologies.
At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s mostinnovative companies unleash their potential. From autonomous cars to life‑saving robots, our digital and software technology experts think outside the box as theyprovide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days arethe same. Capgemini is a global business and technology transformation partner, helping organizations accelerate their dual transformation to address the evolving needs of customers and citizens. With a strong 55‑year heritage and deep industry expertise, Capgemini is trusted by its clients to address the entire breadth of their business needs—from strategy and design to operations. To achieve this, Capgemini draws on the capabilities of its 360,000 team members in more than 50 countries, all driven by the purpose of unleashing human energy through technology for an inclusive and sustainable future. It is a responsible and diverse organization with market‑leading capabilities in digital, cloud, and data.