Design Verification Engineer

ACL Digital; Hyderabad; On-site; INR 600,000 - 1,000,000; Full time

Job summary

An established industry player is actively seeking talented Design Verification Engineers to join their dynamic team in Hyderabad. This role involves leading the verification of DDR memory controllers and developing efficient testbenches using advanced methodologies. With a focus on protocol compliance and formal verification, you will ensure the highest standards in design accuracy. This opportunity offers a vibrant work culture and the chance to contribute to cutting-edge semiconductor projects. If you have a passion for VLSI design and want to make a significant impact in a growing field, this is the perfect role for you.

Qualifications

• 5-20 years of experience in VLSI design verification.
• Strong background in DDR memory controller verification.

Responsibilities

• Lead DDR verification ensuring compliance with DDR standards.
• Develop scalable verification environments using SystemVerilog and UVM.

Skills

DDR Verification

SystemVerilog

UVM

Simulation & Debugging

Formal Verification

Regression Testing

Education

B.E/B.Tech in ECE/EEE

M.E/M.Tech in VLSI/Electronics

Tools

Questa

VCS

ModelSim

Job description

Direct message the job poster from ACL Digital

TA|| 12k Connections || VLSI Recruiter || Actively Hiring PD/ DV/ DFT/ AL/ ALD/ PV/ RTL Engineers with 3 - 20 years of experience || Head Hunter ||…

Experience: 5 Years

Education: B.E/B.Tech in ECE/EEE or M.E/M.Tech in VLSI/Electronics

Roles and Responsibilities

1. DDR Verification: Lead the verification of DDR memory controller and PHY designs, ensuring compliance with DDR standards such as DDR3, DDR4, DDR5, and other memory interface protocols.
2. Testbench Development: Develop and implement scalable, reusable, and efficient verification environments and testbenches for DDR designs using SystemVerilog, UVM (Universal Verification Methodology), and other industry-standard verification methodologies.
3. Protocol Compliance: Ensure the DDR design meets protocol specifications, including command, data, and clock synchronization, read/write cycles, burst transfers, refresh cycles, error handling, and power management.
4. Verification Plan Creation: Develop detailed verification plans based on DDR specifications and requirements, ensuring full coverage of corner cases, timing, and protocol validation.
5. Simulation & Debugging: Run simulations and debug issues using tools such as Questa, VCS, or ModelSim, applying advanced debugging techniques such as waveform analysis, assertion-based verification, and code coverage.
6. Regression Testing: Set up and manage regression testing for DDR functionality to ensure continuous validation and early detection of design issues.
7. Verification Coverage: Achieve high functional and protocol coverage, ensuring that critical aspects of DDR design, including timing constraints, corner cases, and failure scenarios, are thoroughly verified.
8. Formal Verification: Implement formal verification techniques to validate key components of the DDR design, ensuring correctness in timing and data flow, and verifying the most critical operations.

Seniority level

• Mid-Senior level

Employment type

• Full-time

Job function

• Industries: Semiconductor Manufacturing

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