Design Verification Engineer

HCLTech; Bengaluru; On-site; INR 1,200,000 - 2,200,000; Full time

Job summary

HCLTech in Bengaluru, India, is seeking a Design Verification Engineer to verify complex ASIC/SoC designs, develop robust verification environments, and ensure high-quality silicon using industry-standard verification methodologies and tools.

The role emphasizes collaborating with RTL teams, building testbenches, and advancing coverage-driven verification, with opportunities to grow in a fast-paced semiconductor engineering group.

Qualifications

• Bachelor's or master's degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
• 5–10 years of ASIC/SoC verification experience.
• Proficient in SystemVerilog, Verilog, and UVM.
• Experience with industry-standard simulators and debugging.

Responsibilities

• Develop and execute verification plans using UVM/SystemVerilog.
• Design, build, and maintain reusable verification environments and testbenches.
• Perform RTL verification using simulators such as VCS, Xcelium/Incisive, and ModelSim/Questa.
• Debug simulation failures, analyze root causes, and drive issue resolution.
• Work closely with RTL Design teams to resolve functional issues.
• Develop and track code and functional coverage, and verification metrics.
• Participate in design and code reviews and uphold verification best practices.
• Stay updated with emerging verification methodologies and tools.

Skills

SystemVerilog

Verilog

UVM

Digital design

Code coverage

Education

Bachelor's or Master's in EEE/ Electronics/ CE

Tools

VCS

Xcelium/Incisive

ModelSim/Questa

Job description

Job Summary

We are seeking a highly motivated Design Verification Engineer to join our semiconductor engineering team. In this role, you will be responsible for verifying complex ASIC/SoC designs, developing robust verification environments, and ensuring high-quality silicon through industry-standard verification methodologies and tools.

Key Responsibilities

• Develop and execute comprehensive verification plans using UVM/SystemVerilog methodologies.
• Design, build, and maintain reusable verification environments and testbenches.
• Perform RTL verification using industry-standard simulators such as VCS, Xcelium/Incisive, and ModelSim/Questa.
• Debug simulation failures, analyze root causes, and drive issue resolution.
• Work closely with RTL Design teams to identify and resolve functional issues.
• Develop and track code coverage, functional coverage, and verification metrics.
• Participate in design and code reviews while ensuring adherence to verification best practices.
• Stay updated with emerging verification methodologies, tools, and industry trends.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
• 5-10 years of experience in ASIC/SoC Design Verification.
• Strong expertise in SystemVerilog, Verilog, and UVM.
• Solid understanding of digital design fundamentals, including combinational and sequential logic.
• Experience developing and debugging complex verification environments.
• Hands-on experience with industry-standard simulation tools.
• Strong analytical, debugging, and problem-solving skills.
• Excellent communication and collaboration abilities.

Preferred Skills

• Experience with protocols such as AXI, AHB, APB, PCIe, Ethernet, or DDR.
• Knowledge of SystemVerilog Assertions (SVA).
• Scripting experience using Python, Perl, or Shell.
• Experience with coverage-driven verification methodologies.

Why Join Us?

• Opportunity to work on cutting-edge ASIC/SoC technologies.
• Collaborative and fast-paced engineering environment.
• Strong learning, growth, and career advancement opportunities.
• Competitive compensation and comprehensive benefits package.