Design Verification Architect

TYLsemi; India; On-site; INR 4,000,000 - 6,500,000; Full time

Job summary

TYLsemi seeks a seasoned Design Verification Architect to define scalable verification strategies for next-generation SoCs in AI, HPC, and Networking applications.

You will lead reusable verification platforms, drive portability across IP, subsystems, and full-chip levels, and advance high-performance testbenches using UVM and Portable Stimulus. Join a team building next-gen verification platforms leveraging automation and AI-driven methodologies.

Qualifications

• Experience in large-scale SoC verification
• Strong understanding of verification methodologies
• Proficiency in UVM-based testbench development

Responsibilities

• Define and drive the overall verification architecture for large-scale SoCs, ensuring scalability from IP -> subsystem -> full SoC level
• Architect and develop reusable, modular, and portable verification platforms that can be leveraged across multiple chip programs
• Establish methodologies for seamless reuse and portability, including Portable Stimulus (PSS)-based verification flows
• Lead the development of high-performance, coverage-driven testbenches using industry-standard methodologies (e.g., UVM)
• Drive multi-level verification strategies, enabling efficient scaling across Block-level, Multi-block/subsystem level, Full-chip SoC level

Skills

SV/Verilog/VHDL verification

UVM framework

Portable Stimulus (PSS)

SoC verification architecture

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

UVM

Job description

Role Overview

We are seeking a highly experienced

Role Overview

We are seeking a highly experienced Design Verification Architect to lead the definition and execution of scalable, reusable, and high-quality verification strategies for next-generation SoCs targeting AI, HPC, and Networking applications. This role requires deep expertise in verifying large and complex SoCs and a passion for building next-gen verification platforms, leveraging automation, portability, and AI-driven methodologies.

What You’ll Do

• Define and drive the overall verification architecture for large-scale SoCs, ensuring scalability from IP -> subsystem -> full SoC level
• Architect and develop reusable, modular, and portable verification platforms that can be leveraged across multiple chip programs
• Establish methodologies for seamless reuse and portability, including Portable Stimulus (PSS)-based verification flows
• Lead the development of high-performance, coverage-driven testbenches using industry-standard methodologies (e.g., UVM)
• Drive multi-level verification strategies, enabling efficient scaling across:
• Block-level, Multi-block/subsystem level, Full-chip SoC level
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