Design Verification Architect

TylSemi, Inc.; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Benefits offered by this job

Remote-friendly policy

Job summary

TylSemi, Inc. is seeking a highly experienced Design Verification Architect to lead the verification strategy for next-generation SoCs targeting AI/HPC/Networking apps. You will define scalable architectures, reusable platforms, and AI-driven flows to ensure first-pass silicon success.

The role requires deep expertise in SystemVerilog, UVM, and Portable Stimulus, with leadership responsibility across IP to full-chip levels. Bangalore-based with a global, remote-friendly team.

Qualifications

• Bachelor’s/Master’s degree in Electrical Engineering or Computer Engineering or related field.
• 12+ years of experience in Design Verification.
• Strong expertise in SystemVerilog and UVM.
• Experience with Portable Stimulus (PSS) and AI-driven verification.
• Experience with verification architectures for complex SoCs.

Responsibilities

• Define and drive the overall verification architecture for large-scale SoCs.
• Develop reusable, portable verification platforms and methodologies.
• Lead high-performance, coverage-driven testbenches (UVM-based).
• Champion automation, reuse, and AI-driven verification techniques.
• Collaborate with design, architecture, and software teams; mentor DV engineers.

Skills

Design Verification

SystemVerilog

UVM

PSS

AI-driven verification

Assertion-based verification

Cross-IP integration

Education

Electrical Engineering

Computer Engineering

Related field

Job description

About this position

About TylSemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem:how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TylSemi builds thechiplet infrastructure IP— the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why Now

The Market Window

• Moore's Law is dead.2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
• Custom silicon is now mainstream.Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
• IO and power are the bottleneck.Solve hard problems and provide something which is a category in itself.

Translation:We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We WorkNo Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.
• No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

• US team:Bay Area preferred, but we hire the best people regardless of location
• India team:Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

What We Value

• Ownership mindset.You're not here to execute someone else's roadmap. You're here to define it.
• Bias for action.We move fast. Analysis paralysis doesn't fly here.
• Deep technical expertise.This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
• Low ego, high standards.We don't care about titles or politics. We care about results.

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's why you should:

• The market is real.AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.
• The team has done this before.We’ve built and exited semiconductor companies at scale. This isn't our first rodeo.
• The traction is de-risked.We have LOIs, strategic investors, and a clear path to revenue.
• The work is consequential.You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.
• This is the bet.Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.

READY TO JOIN?

Role Overview

We areseekinga highly experiencedDesign Verification Architectto lead the definition and execution of scalable, reusable, and high-quality verification strategies for next-generation SoCs targetingAI, HPC, and Networking applications. This role requires deepexpertisein verifying large and complex SoCs and a passion for building next-gen verificationplatforms,leveragingautomation, portability, and AI-driven methodologies.

WhatYou’llDo

Define and drive theoverall verification architecturefor large-scale SoCs, ensuring scalability fromIP → subsystem → full SoC level Architect and developreusable, modular, and portable verification platformsthat can beleveragedacross multiple chip programs Establish methodologies forseamless reuse and portability, includingPortable Stimulus (PSS)-based verification flows Lead the development ofhigh-performance, coverage-driven testbenchesusing industry-standard methodologies (e.g., UVM) Drivemulti-level verification strategies, enabling efficient scaling across: Block-level, Multi-block/subsystem level, Full-chip SoC level Define and enforceverification quality metrics, coverage closure strategies, and sign-off criteria Champion afail-fast philosophyto detect issues early and improve overall design quality Drive initiatives towardfirst-pass silicon success, minimizing escapes and post-silicon debug effort LeverageAI/ML techniques and AI agentsto: Automate testbench generation Improve stimulus generation and coverage closure Enhance regression efficiency and debug productivity Enable intelligent verification QA and anomaly detection Collaborate closely withdesign, architecture, physical design, and software teamsto ensure alignment and early issue detection Mentor and guide DV teams onbest practices,methodologyadoption, and architectural decisions

WhatWe’reLooking For

Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or related field 12+ years of experience inDesign Verification, with significant exposure tolarge SoC verification Proven experience in defining and deployingverification architectures for complex chips Strongexpertisein: SystemVerilogand UVM Coverage-driven verification (functional + code coverage) Assertion-based verification (SVA) Hands-on experience withPortable Stimulus (PSS)and cross-level stimulus reuse Deep understanding ofSoC architecturesin AI, HPC, or Networking domains Experience withmulti-IP integration challenges, coherency, high-speed interfaces, and large-scale data movement Strong debugging skills and ability to handlecomplex system-level issues

Good to Have

• Experience withAI/ML applications in verification workflows
• Exposure toemulation, prototyping, or hybrid verification platforms
• Familiarity withperformance verification and power-aware verification
• Knowledge of industry-standard protocols (e.g., PCIe, DDR, Ethernet, CXL, UCIe) Experience buildingverification frameworks reused across multiple tape-outs

Key Attributes

• Strong architectural thinking with asystems-level mindset
• High ownership with aquality-first approach
• Bias towardautomation, reuse, and scalability
• Passion for adoptingcutting-edgetechnologies, especially AI-driven verification
• Ability tooperatein a fast-paced environment with afail-fast, learn-fast attitude Excellent collaboration and leadership skills

Success in This Role Looks Like

• High degree ofverification reuse across programs
• Achievement ofcoverage and quality goals within schedule
• Reduction inverification cycle time through automation and AI
• Strongtrack recordoffirst-time silicon success
• Minimal post-silicon escapes and debug cycles