Design Eng

Lattice Semiconductor; Maharashtra; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Lattice Semiconductor in Pune, India, is seeking a Senior Technical Lead with end-to-end ownership of RTL design, microarchitecture, and tapeout for a high-impact processor subsystem. The ideal candidate has 12+ years IC design experience, expert SystemVerilog RTL, and proven ability to drive SoC integration, lint, CDC/RDC/SDC, and DFT across global teams.

You will mentor junior designers, collaborate with architecture and firmware teams, and deliver high-quality, power-conscious designs for

Qualifications

• 12+ years IC design experience, with leadership of a subsystem or complex block.
• Expertise in embedded processor subsystem design (ARM Cortex-M, RISC-V, or equivalent).
• Proficient in SystemVerilog RTL; experience with UPF/CPF power intent.
• Strong SoC integration and IP selection experience.
• Familiarity with DFT-aware flows and tapeouts.

Responsibilities

• Own RTL design and microarchitecture of the processor subsystem.
• Drive RTL implementation and timing, power, and area targets.
• Collaborate with architecture, firmware, and DV/PD teams.
• Mentor and lead junior designers.

Skills

RTL design

SystemVerilog

SoC integration

Microarchitecture

Mentoring

Team leadership

Tools

UPF/CPF power intent

Job description

Lattice Overview
There is energy here… energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Lattice Overview
There is energy here… energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.
Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Job Description

Role specifics:

• This is a full-time individual contributor position located in Pune, India.
• This is a senior technical lead role with end-to-end ownership from microarchitecture through tapeout, working alongside a small, high-impact design team.
• The qualified candidate will be an expert in RTL design, best-in-class coding styles, algorithms, and both Verilog and System Verilog.
• The qualified candidate will be expert in SoC integration and associated quality checks including lint, CDC, RDC, SDC etc.
• The role requires to work with architecture team to define micro architect and design spec.
• The successful candidate will be open and willing to both (a) teach best-known-methods to an existing design team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and an open-minded student.

Responsibilities

• Own RTL design and microarchitecture of the processor subsystem, including embedded MCU cores, bus fabric, and DMA infrastructure
• Work with Architecture team to close the design definition and specs
• Drive RTL implementation, CDC/RDC/SDC closure, and DFT insertion for the subsystemPartner with DV and PD leads to meet chip-level timing, power, and area targets
• Collaborate with firmware team
• Mentor junior designers within the team

Required Qualifications

• 12+ years of IC design experience, with 3+ years leading a subsystem or complex block
• Strong expertise in embedded processor subsystem design (ARM Cortex-M, RISC-V, or equivalent)
• Proficient in SystemVerilog RTL; experience with UPF/CPF power intent
• Proficient in system level modelling
• Expertise in SoC integration, defining micro-architecture and experience of selecting 3rd party IP.
• Familiarity with DFT-aware design and synthesis flows
• Hands-on experience with advanced-node ASIC tapeouts
• Proven ability to work with multiple groups across different sites and time zones.

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

India

Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.

Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com.

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At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.