CPU Physical Design Engineer

Intel Technology India Pvt Ltd; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Intel Technology India Pvt Ltd in Bengaluru, India, is seeking a seasoned CPU Physical Design Engineer to drive RTL-to-GDSII implementation, including synthesis, placement, routing, CTS, and clocking.

You will work with cross‑functional teams to optimize power, performance and area, conduct timing and power integrity checks, and collaborate with EDA vendors to push tool capabilities. On-site role in Bengaluru, India.

Qualifications

• B.Tech or M.Tech in Electrical or Electronics engineering.
• Experience in physical design flow from RTL to GDSII.
• Strong knowledge of CTS, routing, timing, and low‑power techniques.

Responsibilities

• Perform physical design implementation from RTL to GDSII, including synthesis, placement, routing, CTS, and optimization.
• Conduct static timing analysis, power distribution analysis, and reliability verification.
• Collaborate with logic, circuit, architecture, and automation teams to improve microarchitectures and methodologies.
• Work with leading EDA vendors to enhance tool capabilities for high‑speed, low‑power CPU development.
• Optimize designs for power, frequency, and area; drive design methodologies and flow automation for future projects.

Skills

Synthesis

Placement

Clock tree synthesis

Routing

Timing analysis

Power optimization

DFT

Education

B.Tech or M.Tech in Electrical/Electronics

Tools

Synopsys

Cadence

Verilog

VHDL

Job description

CPU Physical Design Engineer Job Details: Job Description: Performs physical design implementation of CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams. Possesses CPU‑specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT. Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, lowpower synthesizable CPU. Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

Qualifications: As a CPU Physical Design Engineer, you will play a pivotal role in implementing high‑performance, low‑power CPU designs from RTL to GDSII. You will focus on detailed processes such as synthesis, placement, routing, timing analysis, and power optimization, enabling designs that meet stringent performance and efficiency targets. Your work will directly influence the success of Intel's next‑generation CPUs and their manufacturing readiness, contributing to innovative advancements in computing technology. You will join a dynamic team dedicated to designing Intel's latest high‑performance CPUs using cutting‑edge technologies. This group focuses on delivering innovative solutions that propel Intel's leadership in the semiconductor industry. Collaborating across multiple domains, the team drives groundbreaking designs that support Intel's mission of creating world‑changing technologies to enrich the lives of every person on Earth.

Be part of a world‑class team driving innovation in CPU design.

Key Responsibilities

• Perform physical design implementation from RTL to GDSII, including synthesis, placement, routing, clock tree synthesis, and optimization.
• Conduct static timing analysis, power distribution analysis, and reliability verification to ensure design convergence and high manufacturability.
• Collaborate with logic, circuit, architecture, and automation teams to improve CPU microarchitectures and design methodologies.
• Work closely with industry‑leading EDA vendors to enhance tool capabilities for high‑speed, low‑power CPU development.
• Optimize designs for power, frequency, and area, ensuring product‑level parameter excellence.
• Participate in developing and improving physical design methodologies and flow automation for future projects.

Qualifications

• B. Tech or M. Tech degree in Electrical, Electronics with 10+ years of relevant experience.
• Technical expertise in synthesis, placement, clock tree synthesis (CTS), and routing tools, particularly using Synopsys and Cadence platforms.
• Proficiency in timing signoff, formal verification, and low‑power design techniques.
• Solid understanding of submicron process node technologies and layout verification methods such as LVS/DRC.
• Skilled in power estimation, power optimization, and power delivery methodologies.

Preferred Qualifications

• Familiarity with scripting languages like Tcl, Perl, and Python for automating physical design workflows.
• Experience with Verilog or VHDL for hardware description and design execution.
• Strong communication skills, both verbal and written, for collaborative problem‑solving.
• Demonstrated ability to work effectively in dynamic environments across geographies.
• Knowledge of innovative feature feasibility studies and SD flow methodologies.

Job Type: Experienced Hire

Shift: Shift 1 (India)

Primary Location: India, Bangalore

Additional Locations:

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust N/A

Work Model for this Role

This role will require an on‑site presence.

Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.