ASIC Verification Engineer

Broadcom; Pune District; On-site; INR 3,000,000 - 5,000,000; Full time

Job summary

Broadcom, Inc. is seeking an experienced verification engineer in Pune to develop comprehensive test plans for Block/Core/SoC features and to write functional coverage.

You will architect scalable verification environments using SystemVerilog and UVM, and build BFMs, checkers, monitors and scoreboards to verify complex semiconductor designs. The role involves designing pseudo-random tests, debugging regression failures in RTL and gate-level simulations, and closing coverage gaps.

Qualifications

• Proficiency in SystemVerilog and verification methodologies (UVM/OVM/VM) is required.
• Strong knowledge of object-oriented programming principles.
• Experience with verification environments and testbench design is essential.
• Knowledge of PCIe, SAS, SATA and AMBA AXI/AHB/APB protocols is desirable.

Responsibilities

• Develop test plans for Block/Core/SoC features and write functional coverage.
• Build verification environments using SystemVerilog and UVM; develop scalable test benches.
• Create BFMs, checkers, monitors and scoreboards; write pseudo-random tests.
• Debug regression failures in RTL/gate-level simulations and optimize tests to fix coverage gaps.
• Document verification strategy including test plans and testbenches.

Skills

SystemVerilog

UVM/OVM/VM

Object-Oriented Programming

Education

Bachelor's or Master's in Electrical Engineering

Job description

Job Description

• Develop Test plans for all features for Block/Core/SOC and Write Functional coverage for these features
• Develop verification environments using System Verilog and UVM Architect and develop scalable and re-usable test benches, using the framework of the verification methodology
• Develop BFMs / Checkers / monitors / Scoreboards
• Build pseudo-random tests to verify and get full Functional coverage
• Debug Regression failures in RTL and Gatelevel simulations, analyze Functional Coverage gaps and improve tests to cover the gaps
• Document verification strategy including Test plans, Testbench, Random tests, etc.

Requirements

• Bachelor’s or Master’s degree in electrical engineering or related degree with 8+ years relevant experience
• Proficiency in System Verilog and Verification Methodologies like UVM/VMM/OVM
• Good command of Object-Oriented Programming principles
• Knowledge of Host interface protocols such as PCIe, SAS, SATA is desired
• Knowledge of AMBA AXI/AHB/APB protocols
• Experience writing Functional Coverage, pseudo random tests
• Flexible to work in any IP/Subsystem/SoC projects
• Capability to work independently and deliver

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Welcome! Thank you for your interest in Broadcom! We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions. For more information please visit our video library and check out our Connected by Broadcom series. Follow us on Linked In Broadcom Inc.