ASIC Program Manager

Anthriq; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Anthriq is developing its first custom ASIC—a multi-core vector processor with a purpose-built instruction set. You will own the master schedule, dependency map, and design freeze decisions, working directly with founders and the architecture team to keep milestones on track.

Expected to lead external partnerships, manage critical-path risks, and ensure delivery across RTL, verification, firmware, and integration stages through tapeout and qualification.

Qualifications

• 8–12 years in semiconductor product development with program management experience on SoC/ASIC programs.
• Experience taking an SoC from RTL to tapeout or silicon bring-up is highly desirable.
• Strong written communication and ability to own milestones and risk registers.
• Ability to coordinate with external partners, foundries, IP vendors, and manufacturing teams.
• Comfort with incomplete information and driving tough conversations early.

Responsibilities

• Own the integrated program plan spanning RTL design, verification, firmware, IP integration, and physical implementation.
• Run weekly reviews, identify coupling points, and drive cross-team alignment to fixed milestones.
• Maintain the dependency map with dates, owners, and acceptance criteria for all deliverables.
• Manage design freeze gates, ECOs, and change control with documented decisions and traceability.
• Coordinate with vendors, IP providers, and manufacturing stakeholders to ensure on-time delivery.

Skills

Program management

Semiconductor

SoC/ASIC

Risk management

Cross-functional leadership

Vendor management

Education

B.E./B.Tech in Electronics, Electrical, Computer Science or related field

Tools

EDA tools

Job description

About Us

Anthriq is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems.

Anthriq Silicon

is our ground-up effort to build a new compute category.

Read more about the Anthriq Silicon Program here: anthriq.com/silicon

About The Role

We are taking our first custom ASIC — a multi-core vector processor with a purpose-built instruction set — from architecture to qualified production silicon on an advanced process node. A program like this has two kinds of gravity. Inside, several engineering tracks move at different speeds and depend on each other in ways that are rarely written down. Outside, a set of partners, IP providers, and manufacturing stakeholders all have their own schedules, and none of them are ours to control. Tapeout happens when both of those are held together by someone whose full-time job it is. That is this role. You will own the master schedule, the dependency map across every internal and external commitment, design freeze and change control, the review cadence, and deliverable acceptance at each milestone. What makes this worth doing: there is one silicon program at this company, and it is this one. You will not be one of nine TPMs reporting into a program office. You will work directly with the founders and the architecture team; you will be in the room where scope and schedule get decided rather than briefed afterward, and your read on what is real versus what is optimistic will move dates that matter.

Responsibilities

Own the integrated program plan

• Maintain one master plan spanning the internal engineering tracks — RTL design, verification, firmware and pre-silicon software, IP integration, physical implementation and every external delivery the program depends on, through tapeout, NPI and qualification.
• Track the critical path weekly and plan backwards from the dates that cannot move, not forwards from what teams would prefer.

Run the cadence and break cross-team blockers

• Run the weekly program review and milestone reviews from a single source of truth.
• Find the coupling points before they bite: a coverage-closure slip gating a design freeze, an incomplete register map stalling firmware, a late IP handover holding up integration, a constraints package that will not survive synthesis. Drive these across team leads rather than reporting them after the fact.
• Hold every track to a shared definition of done, and keep interfaces between teams written down rather than assumed.

Own the dependency map

• Track every commitment the program rests on with a date, an owner, and an acceptance bar: design deliverables, timing constraints and power intent, third-party IP delivery including licensing and documentation, emulation and virtual platform builds, package and test specifications, coverage and quality targets, register maps, and milestone approvals.
• Chase every line, and flag slippage weeks ahead rather than at the review.

Run freeze and change control

• Own the design freeze gates and the ECO log, keeping late change inside agreed limits.
• Route every proposed change through a documented decision — cost, schedule impact, approval. Nothing enters a frozen baseline silently.

Manage external delivery

• Be the program's point of contact for vendors, IP providers, EDA partners and manufacturing-side stakeholders whose timelines we depend on.
• Track what was committed against what has arrived, and read technical status reporting critically rather than accepting the summary slide.
• Know what evidence each milestone requires before it is accepted, and assemble it.

Manage risk and report it straight

• Maintain a live risk register with real mitigations and named owners, and drive contingency planning on tapeout-critical paths.
• Publish a weekly status — schedule, risks, decisions needed, dependencies missed — and elevate to CTO/CEO with a recommendation attached, not just a problem.
• Flag where timelines are at risk from team bandwidth gaps, and feed that into resourcing and hiring conversations.

Requirements

• 8–12 years in semiconductor product development, including 3+ years in a technical program or project management role on SoC/ASIC programs.
• At least one SoC taken from RTL to tapeout, ideally through silicon bring-up. Non-negotiable.
• Working technical fluency across the ASIC lifecycle — design freeze, coverage closure, DFT insertion, synthesis, P&R, STA, EM/IR, DRC/LVS, netlist drops and ECO classes. You will not be hands-on in any one discipline, but you will not be a relay either: you need to ask the next question and know when an estimate is soft.
• Experience holding external partners — design services, foundry, OSAT, IP vendors — to your dates, not just attending their status calls.
• Track record running multi-team programs with competing priorities and a hard external deadline.
• Strong written communication. A large part of this job is a status note clear enough that engineering leads trust it and nobody rewrites it.
• Comfortable with incomplete information, and willing to own the uncomfortable conversation: a slipped date, a thin report, bad news delivered early.
• B.E./B.Tech in Electronics, Electrical, Computer Science or related field.

Preferred

• Prior time at a fabless semiconductor company or chip startup, through a tapeout cycle.
• Advanced-node exposure (7nm or below).
• Third-party IP licensing and delivery coordination.
• Familiarity with hardware emulation and virtual prototyping platforms.
• Contract-linked delivery: SOWs, acceptance criteria tied to technical deliverables.
• PMP/PgMP is a plus, but not a substitute for having run a real program.

Skills: dft insertion,asic design,risk,status,communication,design,ip,it,one,reporting,map,silicon,tapeout