ASIC Engineering Director

Indian Institute of Technology Delhi (IIT Delhi); Hyderabad; On-site; INR 3,000,000 - 4,000,000; Full time

Job summary

The Indian Institute of Technology Delhi (IIT Delhi) is looking for an ASIC Engineering Director based in Hyderabad. This role demands over 20 years of experience in ASIC design and leadership, with a proven track record in leading complex chip designs across various domains.

The successful candidate will define the technical direction for ASIC designs and manage cross-functional teams. Excellent project management and leadership skills are crucial for this position, aiming to drive innovation in edge AI solutions.

Qualifications

• 20+ years of experience in ASIC design and leadership roles.
• Strong project management skills and ability to lead large teams.
• Hands-on experience in chiplets and subsystems development.

Responsibilities

• Define technical direction for ASIC designs.
• Lead design and development of complex IPs and sub-systems.
• Manage cross-functional teams to ensure project success.

Skills

ASIC Front End leadership

Leadership and team management

Chiplets design and integration

Low power design methodologies

Cross-functional collaboration

Job description

ASIC Engineering Director

Job Location: Hyderabad

Experience: 20+ Years

Our game‑changing AI solutions revolutionize what people and businesses can achieve. Ara inference processors combined with our SDK deliver unrivaled deep learning performance at the edge to accelerate and optimize real‑time decision making where every millisecond is critical, and power efficiency is a must. Embedding high-performance AI into edge devices to create a smarter, safer, and more enjoyable world. Edge AI is on the brink of a boom, and Kinara is looking forward to playing a significant role in it.

Key Expertise & Qualifications

• Seasoned ASIC Front End leader with 20 years of cross‑domain experience ranging from architecture, uArch, IP/sub‑systems/SOC/chiplets design/integration, RTL coding, synthesis, CDC, timing, power analysis, system/IP verification, silicon bring‑up.
• Proven track record of leading the design and development of complex IPs, sub‑systems, chiplets for SOCs in the multiple domains like PCIE, USB, UCIE, ARM/x86 CPUs, RISC‑V, VPU/NPU, GPU, LSIO, NOC, fabrics, AMBA buses, DRAM, SD/SDIO/eMMC etc. Responsible for defining the technical direction of ASIC designs and collaborating with cross‑functional teams to ensure successful ASIC implementation.
• Demonstrated strong leadership, project timelines & resources management and team management skills, and the ability to influence the technical strategy of the organization.
• Familiar with ASIC verification methodologies, DFT, physical design and board design which help in influencing cross‑functional teams in getting desired results.
• Excellent execution capabilities to handle multiple domains in multiple projects simultaneously.
• Delivered superior results through team collaboration and diversity of thought. Always open to learn new technologies to grow in technical breadth and depth.
• Managed development of multiple sub‑systems and IPs designed from scratch for Intel IOT (Elkhart Lake), Edge (Reefbay), dVPU/NPU (Arrow LakeR), GPU (DMR‑D), Media (MTL‑D), Smart NIC (Altera NIC), Palm Ridge, Mount Morgan IPU SoCs which are executed in advanced technology nodes of both Intel (18A, 3nm, 5nm) and TSMC (N3e, N5, N6).
• Have hands‑on experience in chiplets, sub‑systems and IP development (micro‑architecture development, 3rd‑party IP integration (Synopsys, Verisilicon, SiFive RISCV, ARM cores etc.), RTL implementation, synthesis, static timing analysis, power analysis, system/IP level verification, FPGA emulation, silicon bring‑up) and SoC integration flows and methodologies.
• Led 30+ engineer design team and have good experience in working with cross‑functional teams and cross‑BU teams across multiple geos, resulting in good collaboration and accelerated time to market.
• Led IP development (RTL design, lint, CDC, synthesis, timing, unit level and system level verification) of various IPs in NVIDIA Tegra SoC processors (from first generation [APX] to ninth generation [Xavier]) and Cisco NIC chips.
• Have good working experience on low power design methodologies (clock gating, power gating, multi‑VT and DVFS) used in mobile SoCs.
• Designed couple of modules in Tegra SoC like DMA engine, SD/SDIO/eMMC5.2 host controller and bus‑bridges for NVIDIA proprietary buses. Worked on architecture, micro‑architecture, RTL design and timing analysis. Familiar with automotive electronics ISO26262 safety requirements.
• Was Executive member from NVIDIA in SD card org and JEDEC (eMMC) forum. Participated in SD/SDIO4.x, SD host4.x and eMMC5.x specification development.
• Working experience with cross‑functional teams like back end, analog I/O pad and SW teams to ensure IP requirements are met at each stage. Have working experience in developing tree build and regression infrastructure.
• Have hands‑on experience in ASIC verification also – test planning, develop directed, random and system‑level (SOC level) test cases; design test bench using SystemVerilog; develop random test environment; execute code coverage & analyse reports, execute gate‑level simulations; execute functional & regression tests.
• Good team player: participated and led the effort of SD4.x/eMMC5.x host controller design and verification. Detail‑oriented go‑getter with fast learning curve and strong analytical, decision making, problem solving, visualizing, negotiating, communication & interpersonal skills.
• Mentored engineers, designed IP/SS schedules with proper staging plan with cross‑team dependencies, identified and solved technical issues, and ensured development of high‑quality products.