ASIC Design Engineer, DMTS/SMTS/MTS

Micron Technology; Hyderabad; On-site; INR 900,000 - 1,500,000; Full time

Job summary

Micron Technology invites experienced engineers to join its design enablement teams in Hyderabad, India. You will drive CAD tool deployment, automation, and signoff workflows for NAND, DRAM, and SoC products, enabling scalable, high‑quality silicon.

The role emphasizes AI‑assisted engineering, multi‑corner timing, and collaboration across architecture, layout, and verification to ensure manufacturability. A BS/MS in EE/CE and strong scripting are expected.

Qualifications

• Bachelor's or Master's degree in Electrical/Computer Engineering or related field.
• Hands‑on experience with industry‑standard EDA environments for implementation and signoff.
• Proficiency in scripting languages and ability to automate engineering workflows.

Responsibilities

• Own CAD tools, automation frameworks, and design flows for advanced semiconductor products.
• Develop and maintain infrastructure for build capture, layout, simulation, verification, and signoff workflows.
• Create automation scripts using Python, Tcl, SKILL, Shell, Perl, C/C++, Java, or Lisp.
• Lead timing signoff and DFT strategies across multi‑mode/multi‑corner scenarios.
• Collaborate with cross‑functional teams to ensure manufacturability and silicon quality.

Skills

Python scripting

Unix/Linux

VLSI fundamentals

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Cadence Innovus

Cadence Virtuoso

Synopsys ICC2

Synopsys PrimeTime

Siemens Tessent

Cadence Tempus

Cadence Modus

Job description

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Key Responsibilities

Design and CAD Enablement

• Own the development, deployment, and support of scalable CAD tools, automation frameworks, design flows, and methodologies for NAND, DRAM, HBM, SoC, mixed-signal, and other advanced semiconductor products.
• Develop, improve, and maintain infrastructure for circuit build capture, layout, simulation, characterization, implementation, physical verification, and signoff workflows.
• Create robust software and scripts using Python, Tcl, SKILL, Shell, Perl, C/C++, Java, Lisp, or related languages to automate engineering workflows, analytics, and quality checks.
• Evaluate and integrate advanced EDA technologies, AI-assisted engineering solutions, and emerging methodologies to improve productivity, scalability, and silicon quality.
• Validated ability to demonstrate AI‑assisted (vibe) coding techniques to improve efficiency or automate design and analysis methodologies Leverage AI tools to automate the tools and workflow Applying Artificial Intelligence in workflows to improve build efficiency
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• Lead implementation and signoff activities across physical design, static timing analysis, and design for test for complex digital, memory, SoC, or mixed-signal products.
• Drive floor planning, power planning, placement, clock tree synthesis, routing, optimization, timing closure, and physical verification to meet power, performance, area, reliability, and schedule targets.
• Own multi-mode, multi-corner timing signoff, including constraints, setup and hold analysis, timing exceptions, signal integrity, ECOs, and closure across implementation achievements.
• Develop and implement DFT strategies, including scan insertion, ATPG, MBIST, LBIST, compression, verification, and silicon bring-up support to achieve manufacturing test coverage goals
• Analyze and resolve congestion, IR drop, electromigration, clocking, signal integrity, and implementation issues throughout the design cycle.

Analog and Custom Layout

• Give to next‑generation products through the design, optimization, and physical implementation of memory, logic, and analog circuits
• Lead custom layout activities, including floor planning, device placement, routing, matching, parasitic‑aware optimization, and layout quality reviews.
• Perform parasitic extraction and modeling, and support circuit simulation, design validation, reticle experiments, tape‑out revisions, and post‑layout correlation.
• Complete layout and circuit verification using industry‑standard simulation, extraction, DRC, LVS, and reliability verification tools

Technical Leadership and Teamwork

• Partner with architecture, RTL, circuit design, verification, methodology, process technology, modeling, standards, product engineering, probe, assembly, test, and marketing teams to ensure design readiness and manufacturability Drive standardization, documentation, training, user support, best‑practice adoption, and continuous methodology improvement across global engineering teams.
• Provide technical leadership, mentorship, and subject‑matter expertise; influence tool, flow, and methodology roadmaps while solving complex multi‑functional challenges.
• Support tape‑out, first‑pass silicon success, production ramp, and interpersonal learning through focused execution and effective collaboration.

Qualifications

• Bachelor's or Master's degree or equivalent experience in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent proven experience. Strong knowledge of VLSI and CMOS fundamentals, semiconductor build methodologies, and tradeoffs involving power consumption, efficiency, size, dependability, and manufacturability.
• Hands‑on experience with industry‑standard EDA environments for implementation, timing, test, simulation, extraction, layout, verification, and signoff. Relevant tools may include Cadence Innovus and Virtuoso, Synopsys ICC2 and PrimeTime, Siemens Tessent, Cadence Tempus and Modus, or equivalent platforms.
• Proficiency in Unix/Linux environments and one or more engineering programming or scripting languages such as Python, Tcl, SKILL, Shell, Perl, C/C++, Java, or Lisp. Demonstrated ability to develop maintainable automation, debug complex design and flow issues, analyze engineering data, and drive designs to closure.

About Micron Technology, Inc.

We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high‑performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

To request assistance with the application process and/or for reasonable accommodations, please contact [e-mail]

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.