ASIC Design and STA Engineer

NVIDIA Gruppe; Bengaluru; On-site; INR 133,920 - 200,880; Full time

Job summary

NVIDIA Gruppe is seeking a top-notch ASIC STA Engineer to enhance our Networking Silicon engineering team in Bengaluru. The role focuses on the full chip and chiplet level STA convergence and optimizing flows.

The ideal candidate has a B.Sc./M.Sc. in Electrical or Computer Engineering, with at least 3 years of relevant experience and proficiency in EDA tools like Synopsys and Cadence.

Your role will also involve close collaboration with logic design and DFT engineers.

Qualifications

• 3+ years of experience in physical design and STA.
• Proven experience in RTL2GDS and STA design and convergence.
• Hands-on STA experience from early stages to signoff.

Responsibilities

• Charge of full chip and/or chiplet level STA convergence.
• Participate in top level floor plan and clock planning.
• Optimize CAD signoff flows and methodologies.

Skills

Physical design and STA

RTL2GDS design and convergence

Team collaboration

Education

B.SC./M.SC. in Electrical Engineering/Computer Engineering

Tools

Synopsys

Cadence

Synopsis Primetime

Job description

NVIDIA is looking for a best‑in‑class ASIC STA Engineer to join our outstanding Networking Silicon engineering team, developing high‑speed communication devices for AI platforms.

Responsibilities

• Be in charge of full chip and/or chiplet level STA convergence from early stages to signoff.
• Take part in top level floor plan and clock planning.
• Optimize, together with CAD signoff flows and methodologies.
• Digital Partitions and analog IPs timing integration, giving feedback to PD/RTL and driving convergence.
• Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including their optimization for runtime and efficiency.

Qualifications

• B.SC./ M.SC. in Electrical Engineering/Computer Engineering.
• 3+ years of experience in physical design and STA.
• Proven experience in RTL2GDS and STA design and convergence.
• Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
• Hands on STA experience from early stages to signoff using Synopsis Primetime. Deep knowledge in timing concepts required.
• Great teammate.

Join us and become the engineer you always wanted to be.