ASIC Design and STA Engineer

NVIDIA Corporation; Hyderabad; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

NVIDIA is seeking an ASIC STA Engineer for its Networking Silicon team in India (Bengaluru or Hyderabad). You will own STA convergence from early design stages to signoff, participate in floor planning and clock planning, and optimize timing with CAD signoff flows.

You will collaborate with logic design and DFT teams to implement constraints for multiple work modes, ensuring robust performance and efficiency for AI platforms.

Qualifications

• Be in charge of full chip and/or chiplet level STA convergence from early stages to signoff.
• Collaborate on top level floor planning and clock planning.
• Optimize with CAD signoff flows and methodologies.
• Timing integration for digital partitions and analog IPs with feedback to PD/RTL.
• Work with logic design and DFT engineers to define constraints for various modes.

Responsibilities

• Contribute to timing convergence across chip blocks and ensure signoff readiness.
• Interface with CAD tools to implement timing constraints and optimize runtime and area.

Skills

STA engineering

RTL2GDS

Primetime

EDA tools

Timing convergence

Education

B.SC./ M.SC. Electrical Engineering or Computer Engineering

Tools

Synopsys Cadence Tools

Synopsys Primetime

Job description

## ASIC Design and STA EngineerApplylocations: India, Bengaluru: India, Hyderabadtime type: Full timeposted on: Posted Todayjob requisition id: JR2021789NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!NVIDIA is looking for a best-in-class ASIC STA Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency for today's AI platforms! Come and take a part in designing our groundbreaking large scale and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.**What you will be doing:*** Be in charge of full chip and/or chiplet level STA convergence from early stages to signoff.* Take part in top level floor plan and clock planning.* Optimize, together with CAD signoff flows and methodologies.* Digital Partitions' and analog IPs' timing integration, giving feedback to PD/RTL and driving convergence.* Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including their optimization for runtime and efficiency.**What we need to see:*** B.SC./ M.SC. in Electrical Engineering/Computer Engineering.* 3+ years of experience in physical design and STA* Proven experience in RTL2GDS and STA design and convergence* Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.)* Hands on STA experience from early stages to signoff using Synopsis Primetime. Deep knowledge in timing concepts required.* Great teammate.NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!#LI-Hybrid