Staff SW Pre-Silicon System Verification Engineer

Evollabs; Hyderabad; On-site; INR 3,600,000 - 6,400,000; Full time

Job summary

Evollabs is seeking a Staff SW Pre-Silicon System Verification Engineer in Hyderabad, India. You will build software infrastructure and testbenches to verify an AI ASIC, bridging RTL with system software and firmware.

You will drive pre-silicon validation, register modelling, and coverage-driven verification across cross-functional teams. You will develop C/C++ test sequences, manage DPI-C interfaces, and collaborate on UVM sequences, with a strong emphasis on debugging, timing, and protocol

Qualifications

• 5+ years in pre-silicon verification or system-level modelling for SoCs/accelerators.
• RTL reading skills and SystemVerilog DPI-C interface design.
• Proficient in C/C++ testbenches and UML/UVM usage.
• Experience with AMBA AXI/APB protocols and protocol debugging.
• Familiarity with waveform analysis and industry simulators.

Responsibilities

• Develop and maintain System Verification Plan and testbenches.
• Own C/C++-based system-level test infrastructure and DPI-C interfaces.
• Collaborate with UVM teams, RTL designers, and software engineers.
• Analyze waveforms to debug hardware–software interactions and timing issues.
• Create stimulus generators and regression frameworks with coverage tracking.
• Validate host-driver to firmware interfaces and data-path verification.

Education

Bachelor's degree in Electrical Engineering, Computer Science, or related field

Tools

VCS

Questa

Xcelium

Verdi

DVE

Simvision

Job description

Staff SW Pre-Silicon System Verification Engineer

We are building a next-generation AI ASIC and need to validate it comprehensively before tape‑out. As a Staff System‑Level Verification Engineer, you will develop the software infrastructure, models, and testbenches that prove our hardware design meets specifications and integrates seamlessly with the full software stack—from firmware to host drivers.

You will operate at the critical intersection of RTL design and system software, creating pre‑silicon verification environments that catch bugs early, validate programming interfaces, and enable firmware and driver development months before silicon arrives. Working within a collaborative cross‑functional team of UVM verification engineers, RTL designers, architects, and software developers, you will anchor the system‑software verification layer and directly influence tape‑out confidence and time‑to‑market.

Responsibilities

• Develop and maintain System Verification Plan
• Create and validate programming sequences for hardware initialization, configuration, and runtime operations
• Own the C/C++-based system‑level test infrastructure and SystemVerilog DPI-C interfaces
• Collaborate with the UVM team on sequence integration, coverage alignment, and regression interoperability
• Analyze simulation waveforms to debug hardware‑software interactions, protocol violations, and timing issues
• Implement verification testbenches covering functional scenarios, corner cases, error injection, and recovery paths
• Collaborate with RTL designers to reproduce bugs, validate fixes, and close verification gaps
• Create stimulus generators and reference models for data‑path validation and result checking
• Build regression frameworks with coverage tracking and automated reporting
• Develop C/C++ test sequences that execute representative AI workloads (provided by architecture/ML teams), including graph dispatch, tensor movement, and synchronization.
• Validate the command and control interface (e.g., mailboxes, doorbells) from the host driver to the accelerator's firmware and hardware schedulers.

Minimum Qualifications

• 5+ years in pre‑silicon verification, hardware–software co‑verification, or system‑level modeling for SoCs or accelerators
• Proficiency in reading RTL (Verilog/SystemVerilog) and co‑designing SystemVerilog DPI-C interfaces to connect C/C++ testbenches with the UVM simulation environment.
• Proven experience developing register models and validating programming sequences against RTL across multiple subsystems
• Hands‑on expertise with AMBA protocols (AXI/APB): outstanding transactions, ordering rules, back‑pressure, error responses
• Proficiency analyzing waveforms to root‑cause protocol, ordering, and timing issues
• Solid C/C++ for testbench infrastructure, reference models, and verification components; Python/Perl/Tcl for automation
• Experience with industry simulators (VCS/Questa/Xcelium) and waveform viewers (Verdi/DVE/Simvision)
• Familiarity with at least one of: PCIe Gen5/Gen6 (PF/VF, SR‑IOV), Ethernet 400/800G with RoCEv2, HBM memory controllers, NoC topologies/QoS, RISC‑V firmware bring‑up
• Excellent debug methodology: clear hypotheses, minimal reproductions, crisp bug reports and fixes

Preferred Qualifications

• Pre‑silicon verification experience on AI/ML accelerators, GPUs, or high‑performance compute engines
• Experience driving UVM sequences and monitors from a C/C++ test harness.
• PCIe, SR‑IOV/virtualization, Ethernet/RDMA, HBM/DDR controllers, or NoC verification; experience with protocol compliance suites and VIPs
• Experience with FPGA prototyping for pre‑silicon validation
• Firmware or Linux driver development background enabling deep understanding of software requirements
• Exposure to security verification concepts such as fault injection or secure boot validation

What Success Looks Like

• >>95% functional coverage on user‑defined scenarios and error recovery paths, as defined in the System Verification Plan
• IO and NoC infrastructure validated against key use cases (single-card inference/training, multi-card with RDMA)
• System‑level regression runs full AI workload scenarios (e.g., model graph initialization, execution, and result readback) using the C/C++ test infrastructure.
• Nightly regressions with coverage tracking and trend dashboards; clear metrics track closure by subsystem and use case
• Documentation (register specs, programming guides, timing diagrams, bring‑up checklists) unblocks parallel software development

Nice‑to‑Have Tooling

• Version control & CI: Git, Jenkins, GitLab CI, regression management systems