Senior SerDes & High-Speed Analog Silicon Engineer

AMD

Ballyerra

On-site

EUR 120,000 - 160,000

Full time

3 days ago
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Job summary

AMD in Ireland is hiring a Senior Staff Silicon Design Engineer (SMTS level) to work on high-speed analog circuits for SerDes development on advanced CMOS nodes. You will design and verify analog blocks, collaborate with SerDes teams, and contribute to the performance and reliability targets of AMD CPU/GPU/FPGA products.

The role emphasizes low-power design, layout-aware verification, and cross-site teamwork, with opportunities to shape next-generation high-speed links.

Qualifications

  • Strong analog circuit design and analysis capabilities.
  • Experience with circuit floor planning.
  • Familiar with the impact of layout effects on circuit performance.
  • Programming/scripting skills helpful.
  • Ability to work with cross-site teams.
  • Silicon debug, verification and characterization experience.
  • Excellent interpersonal skills.

Responsibilities

  • Analog circuit design for SerDes PHY development to meet block level design specifications.
  • Verify circuit designs for performance, reliability and compatibility.
  • Present design progress to peers.
  • Participate in design reviews to identify issues and learn.
  • Collaborate with SerDes teams across sites/time zones.
  • Feed back performance data to architecture team for system modeling.
  • Support silicon bring-up and debugging.
  • Assist with test and characterization.

Skills

Analog circuit design
Scripting skills
Layout effects understanding
Circuit floor planning
High-speed circuit design
Silicon debug/verification
Interpersonal/teamwork

Education

Bachelor's or Master's degree in Electronic/Electrical Engineering

Job description

AMD in Ireland is hiring a Senior Staff Silicon Design Engineer (SMTS level) to work on high-speed analog circuits for SerDes development on advanced CMOS nodes. You will design and verify analog blocks, collaborate with SerDes teams, and contribute to the performance and reliability targets of AMD CPU/GPU/FPGA products.

The role emphasizes low-power design, layout-aware verification, and cross-site teamwork, with opportunities to shape next-generation high-speed links.

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