Senior Lithography and Photomask Process Engineer

Intel Corporation; Leixlip; On-site; EUR 103,000 - 161,000; Full time

Job summary

Intel Corporation in Ireland, Leixlip, is seeking an experienced process engineer to lead photomask and reticle operations, including pellicle development and lifecycle management for EUV and DUV toolsets. You will partner with Scanner/Litho, Reticle Design, and Yield teams to diagnose excursions and accelerate technology transitions.

The role emphasizes yield ramp, root-cause analysis, SOPs, and direct collaboration with lithography suppliers.

Qualifications

• MS with 8+ years in foundry or PhD in a related semiconductor field.
• 8+ years hands-on process engineering in lithography and photomask/reticle tech.
• In-depth mask fabrication, metrology, pellicle tech, and defect inspection knowledge.
• Proficiency with DUV and EUV exposure systems, track integration, and CD metrology.
• Advanced use of SPC/DOE and yield analytics tools (JMP, Python, MATLAB).
• Leadership, cross-functional collaboration, and executive communication.

Responsibilities

• Oversee photomask inbound QC, pellicle integrity, reticle qualification and lifecycle.
• Drive EUV pellicle development and optimize pellicle/reticle usage and yield.
• Collaborate with Scanner/Litho, Reticle Design, Thin Films, and Yield teams to diagnose excursions.
• Lead RCFA for yield-limiting defects during node development and high-volume manufacturing.
• Mentor engineers, establish SOPs, and liaise with lithography equipment suppliers.

Skills

SPC & DOE

Yield analytics

Python/MATLAB

Leadership

Cross-functional collaboration

Education

M.S. with 8+ years of foundry experience or Ph.D. in related semiconductor discipline

Tools

DUV (ArFi / 193nm immersion)

EUV exposure systems (ASML Twinscan / NXE)

Mask metrology

Pellicle technology

Reticle degradation mechanisms

Mask defect inspection platforms

Job description

Key Responsibilities

• Photomask and Reticle Operations: Oversee photomask incoming quality control, pellicle integrity, reticle qualification protocols, and reticle lifecycle management across advanced EUV and DUV toolsets.
• Advanced Pellicle Development: Drive next gen EUV pellicle development, material optimization for enhanced transmission, stability, defect mitigation and overall yield improvement. Optimize reticle usage, inspection and disposition strategies over life cycle.
• Cross-Functional Process Integration: Partner closely with Scanner/Litho teams, Reticle Design, Thin Films, Etch, and Yield Enhancement engineering teams to diagnose patterning excursions and accelerate technology transitions.
• Yield Ramp and Excursion Containment: Lead root cause failure analysis (RCFA) for yield-limiting lithography and reticle-related defects during new process node development and high-volume manufacturing (HVM).
• Technical Mentorship and Industry Engagement: Provide technical leadership to junior and mid-level process engineers, establish standard operating procedures (SOPs), and collaborate directly with leading lithography and mask equipment suppliers.

Qualifications:

• Education: M.S. with 8+ years of foundry experience or Ph.D. of Foundry experience in Electrical Engineering, Chemical Engineering, Materials Science, Physics, Optics, Microelectronics, or a related semiconductor engineering discipline.
• Experience: 8+ years of hands-on process engineering experience in advanced semiconductor lithography and photomask/reticle technologies within high-volume manufacturing (HVM) or advanced technology development fabs.
• Photomask and Reticle Expertise: In-depth knowledge of mask fabrication, mask metrology, aerial image modeling, pellicle technology, reticle degradation mechanisms, and mask defect inspection platforms.
• Lithography Toolset and Process Knowledge: Proven proficiency across DUV (ArFi / 193nm immersion) and EUV exposure systems (ASML Twinscan / NXE platforms), track integration, and advanced CD metrology.
• Analytical and Statistical Mastery: Advanced proficiency with Statistical Process Control (SPC), Design of Experiments (DOE), yield analytics platforms, JMP, Python, or MATLAB for complex data modeling and multivariate analysis.
• Leadership and Communication: Track record of driving cross-functional taskforces, writing comprehensive technical documentation, and delivering executive briefings on process yield, tool performance, and quality enhancements.

We invite you to bring your technical expertise and innovative vision to Intel Foundry, where your work will drive the next generation of semiconductor technology. Join us to make an impact and advance your career in a dynamic, collaborative environment.

Job Type: Experienced Hire Shift: Shift 1 (Ireland) Primary Location: Ireland, Leixlip Additional Locations:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Compensation

Position of Trust N/A EU Salary We offer a total compensation package that ranks among the best in the industry.

Annual Salary Range for this job which could be performed in Ireland is: €103,000.00 - €161,000.00 The compensation range displayed in this posting reflects the minimum and maximum target compensation for this position. Within this range, individual pay is determined by job related skills, experience, and relevant education, training. As part of our total compensation approach, the final offer may include additional pay components and benefits. Your recruiting team will share the confirmed base salary along with any applicable total compensation elements upon employment offer delivery.

Work Model for this Role

• Job posting details (such as work model, location or time type) are subject to change.
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