Principal RTL Design Engineer - SoC Performance

Cadence; Cork; On-site; EUR 120,000 - 180,000; Full time

Benefits offered by this job

Travel: 10%

Job summary

Cadence invites an exceptional Principal Digital Implementation Engineer to join the Performance Solutions Group. The role involves developing and integrating high-performance RTL for complex SoCs and silicon platforms, working from architecture requirements through RTL implementation, simulations, synthesis, and handoff to downstream teams.

You will collaborate with architects, verification, and physical design engineers to optimize timing, power, and area while upholding design quality.

Qualifications

• Bachelor’s or Master’s degree in Electrical or Computer Engineering.
• 10+ years of RTL/ASIC design experience.
• Proficiency in Verilog or SystemVerilog.
• Experience with ASIC/FPGA synthesis and debugging.

Responsibilities

• Design, implement, and integrate high-quality synthesizable RTL using SystemVerilog.
• Translate architectural specifications into robust microarchitectures and RTL implementations.
• Work with architects and senior engineers to understand functional and performance requirements.
• Develop RTL that meets requirements for performance, power, area, and functionality.
• Participate in RTL design reviews and contribute to design methodology and coding standards.
• Develop and maintain unit-level and block-level test environments in collaboration with verification engineers.
• Debug functional issues using simulation, waveform analysis, assertions, and other verification tools.
• Work with verification teams to identify, reproduce, and resolve RTL design issues.
• Collaborate with physical design engineers to understand and address timing, area, power, and implementation constraints.
• Support synthesis, timing analysis, linting, CDC analysis, and other front-end quality checks.
• Contribute to integration of internally developed and third‑party IP.
• Help investigate and resolve issues encountered during integration and downstream implementation.
• Document design decisions, interfaces, microarchitecture, implementation details and reviews within the PSG Quality Management System (QMS)
• Contribute to continuous improvement of RTL methodologies, automation, and development flows.
• Work alongside senior engineers to develop solutions to challenging customer and internal silicon problems.

Skills

RTL/ASIC design

Verilog/SystemVerilog

Digital logic design

Synchronous design

Communication skills

Education

Bachelor's or Master's degree in Electrical/Computer Engineering

Tools

Cadence tools

Job description

Cadence invites an exceptional Principal Digital Implementation Engineer to join the Performance Solutions Group. The role involves developing and integrating high-performance RTL for complex SoCs and silicon platforms, working from architecture requirements through RTL implementation, simulations, synthesis, and handoff to downstream teams.

You will collaborate with architects, verification, and physical design engineers to optimize timing, power, and area while upholding design quality.