Power Integrity Engineer – PDN/EMIR for ASICs

Qualcomm; Cork; On-site; EUR 70,000 - 110,000; Full time

Benefits offered by this job

Relocation assistance

Stock options

Pension plan

Medical insurance

Education assistance

Job summary

Qualcomm is seeking a PDN/EMIR Engineer in Cork, Ireland, to perform PDN analyses (IR-drop, EM) and contribute to sign-off for high-performance ASICs. You will develop new techniques, work with design and Physical Design teams, and drive PDN robustness across SOCs.

The role emphasizes automation, scripting in Python/TCL/Perl, and collaboration with cross-functional teams to meet Vmin specs and ensure power integrity closure.

Qualifications

• Bachelor's degree in Science, Engineering, or related field with 4+ years of ASIC experience.
• Master's degree in Science, Engineering, or related field with 3+ years of ASIC experience.
• PhD in Science, Engineering, or related field with 2+ years of ASIC experience.

Responsibilities

• Performing PDN checks such as IR-drop, ESD and electromigration (EM) for complex cores and full-chip SOCs.
• Developing new techniques and methodologies for PDN analyses, optimization and sign-off.
• Working with design team on selecting use-cases for power integrity sign-off and performing power analysis on PD gate netlists.
• Collaborating with Physical Design and STA teams for Vmin assessment and optimization.
• Ensuring compliance with power integrity signoff checklists and criteria.
• Automation for power and PDN data mining and processing.
• Anticipating and resolving PDN issues to ensure smooth project execution.

Skills

Power integrity

PDN/EMIR

Automation scripting

Python

TCL

Perl

Cross-functional collaboration

Electromigration

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

RedHawk

RHSC

Voltus

PTPX

Job description

Qualcomm is seeking a PDN/EMIR Engineer in Cork, Ireland, to perform PDN analyses (IR-drop, EM) and contribute to sign-off for high-performance ASICs. You will develop new techniques, work with design and Physical Design teams, and drive PDN robustness across SOCs.

The role emphasizes automation, scripting in Python/TCL/Perl, and collaboration with cross-functional teams to meet Vmin specs and ensure power integrity closure.