Lead EDA Verification Engineer — Signoff & Strategy

Analog Devices; Munster; On-site; EUR 90,000 - 140,000; Full time

Job summary

Analog Devices, Inc. in Ireland is seeking a Lead EDA Engineer to lead backend physical verification strategy and design enablement across analog and mixed-signal programs.

The role covers Calibre-based signoff, rule integration, and tapeout readiness, shaping flows, debugging complex issues, and driving efficiency across multi-site teams.

You will mentor engineers, automate verification tasks, and collaborate with layout, CAD, and test teams to ensure successful tapeouts on next-generation nodes.

Qualifications

• Lead backend physical verification and signoff flows for ICs.
• Define and debug complex runsets, rule decks, and extraction flows.
• Collaborate with foundries on rules and process nodes.
• Develop internal tools and automation to improve efficiency.
• Mentor engineers and establish verification best practices.

Responsibilities

• Serve as technical authority for Calibre-based verification and signoff.
• Drive foundry rule intake, validation, and release readiness for new nodes.
• Own final tapeout signoff and waiver governance, antenna issue closure.
• Collaborate with analog layout, CAD, and design teams to prevent risks.
• Build dashboards and tooling to improve visibility and resource use.

Skills

Physical Verification Leadership

Calibre expertise

Node experience (16nm/5nm/4nm)

Debug and risk escalation

Python/Tcl/Shell scripting

Linux-based EDA environments

Cross-functional collaboration

Analog layout understanding

Education

BS or MS in Electrical Engineering or related field

10+ years of related experience

Tools

Mentor Calibre

Cadence Virtuoso (SKILL/Bin dkeys)

Perforce for design data management

GUI/tools for dashboards

Linux compute infrastructure

Job description

Analog Devices, Inc. in Ireland is seeking a Lead EDA Engineer to lead backend physical verification strategy and design enablement across analog and mixed-signal programs.

The role covers Calibre-based signoff, rule integration, and tapeout readiness, shaping flows, debugging complex issues, and driving efficiency across multi-site teams.

You will mentor engineers, automate verification tasks, and collaborate with layout, CAD, and test teams to ensure successful tapeouts on next-generation nodes.