Design Engineer Intern: RTL, Verilog & EDA in Cork

Cadence Design Systems; Cork; On-site; EUR 24,000 - 32,000; Full time

Job summary

Cadence Design Systems in Cork, Ireland, invites applications for a Design Engineering Intern to join the Tensilica CPU Processor Team. This role focuses on RTL implementation of microprocessor cores and DSPs, supporting timing, area, and power goals within our R&D group.

The internship provides hands-on work with Verilog RTL, test planning, diagnostics, and collaboration with Design Verification and EDA teams while you pursue a degree in Electrical or Computer Engineering.

Qualifications

• Deep understanding of Digital Design Fundamentals.
• Excellent automation skills using Tcl, Perl, shell scripting.
• Excellent oral and written communications skills.

Responsibilities

• RTL implementation of microprocessor cores and DSPs; meet timing, area, and power goals.
• Develop test plans, write functional diagnostics, debug failures, and analyze coverage.
• Collaborate with Design Verification and EDA teams.

Skills

Digital Design Fundamentals

Excellent oral and written komunik

Education

Bachelor’s/Master’s in Electrical or Computer Engineering

Tools

Tcl

Perl

Shell scripting

Job description

Cadence Design Systems in Cork, Ireland, invites applications for a Design Engineering Intern to join the Tensilica CPU Processor Team. This role focuses on RTL implementation of microprocessor cores and DSPs, supporting timing, area, and power goals within our R&D group.

The internship provides hands-on work with Verilog RTL, test planning, diagnostics, and collaboration with Design Verification and EDA teams while you pursue a degree in Electrical or Computer Engineering.