Senior FPGA Design Engineer — SoC, IP, Transceivers

BLT - The Embedded Experts; Yaur; On-site; IDR 1,963,584,000 - 3,034,630,000; Full time

Benefits offered by this job

Medical, dental, and vision

401K

Life insurance

Short and long-term disability

Paid vacation

Holidays/PTO

A flexible work environment

Individual, private offices for all}}

Job summary

BLT - The Embedded Experts seeks an FPGA Design Engineer for on-site roles in Melbourne, FL or Columbia, MD. The candidate should have 5+ years of FPGA/SoC design experience, a BSEE or BSCE, and US citizenship with eligibility for clearance.

You will design, integrate, and test advanced HDL (VHDL/Verilog/SystemVerilog) designs, emphasize timing closure, Synchronous Design, and use Vivado/Vitis, IP Integrator, and rich IP cores.

Qualifications

• 5+ years of FPGA/SoC design and development experience.
• Bachelor's in electrical/EC/related field; advanced degree preferred.
• US citizenship and ability to obtain clearance.

Responsibilities

• Design, integrate, and test FPGA/SoC systems in fast-paced cycles.
• Ensure timing closure and HDL quality across projects.
• Collaborate on IP integration and verification activities.

Skills

Synchronous Design

Timing Closure

Vivado / Vitis

Simulation

IP Integrator / Block Design

VHDL / Verilog / SystemVerilog

Multigigabit Transceivers

IP Integration

Embedded Design

Education

BSEE or BSCE

MSEE or MSCE preferred

Tools

AMD Xilinx UltraScale+ MPSoC or RFSoC

MicroChip / Microsemi / Actel

Intel / Altera

Lattice

Tcl scripting language

High-Speed Protocols

Job description

BLT - The Embedded Experts seeks an FPGA Design Engineer for on-site roles in Melbourne, FL or Columbia, MD. The candidate should have 5+ years of FPGA/SoC design experience, a BSEE or BSCE, and US citizenship with eligibility for clearance.

You will design, integrate, and test advanced HDL (VHDL/Verilog/SystemVerilog) designs, emphasize timing closure, Synchronous Design, and use Vivado/Vitis, IP Integrator, and rich IP cores.