Senior IC Layout Engineer #10248

Anradus Pte. Ltd.; Hong Kong; On-site; HKD 679,000 - 1,110,000; Full time

Benefits offered by this job

Meal allowance

Medical & dental benefits

VB included

Job summary

Anradus Pte. Ltd. is seeking a Senior IC Layout Engineer to drive layout activities for advanced semiconductor projects. The role focuses on floor planning, device placement, and robust routing to meet SI/PI targets.

You will verify designs with DRC/LVS checks and collaborate on post-layout optimizations while mentoring junior engineers. This position is on-site in Singapore and offers comprehensive benefits.

Qualifications

• Diploma or Bachelor’s degree in Electrical Engineering, Computer Engineering, Electronics Engineering or equivalent.
• At least 6 years of hands-on layout engineering experience.
• Experience with technology nodes below 16nm, high-speed or RF layout.
• Experience with Cadence SKILL or equivalent tools for PCell development and automation.
• Good understanding of analog/digital chip-top integration and CAD setup for LVS/DRC.

Responsibilities

• Develop layout designs based on schematic presentations.
• Perform floor planning and device placement.
• Route power and signals; optimize SI/PI.
• Conduct DRC/LVS/ERC/ANT/ESD/PERC/LVL checks.
• Ensure layouts pass DRC and LVS requirements.
• Prepare layout materials and conduct reviews.
• Support layout quality improvements and methodologies.
• Mentor junior layout engineers.
• Participate in post-layout adjustments and block/IP activities.
• Apply AMS layout fundamentals, EMIR, RC delay, decoupling capacitors, latch-up.
• Other ad-hoc duties as assigned.

Skills

Layout engineering

CAD tools (Cadence SKILL, PCell)

Scripting (Perl, Python, TCL)

AMS layout fundamentals

RF/high-speed layout

Mentoring/leadership

Education

Bachelor’s or Diploma in Electrical/Computer/Electronics Engineering

Tools

Cadence SKILL

Perl

Python

TCL

Job description

Senior IC Layout Engineer #10248

Industry/ Organization Type
Semiconductor

Position Title
Senior IC Layout Engineer

Working Location
Ang Mo Kio

Working Hours
5 Days (Monday – Friday, 9:00 AM – 6:00 PM)

Salary Package
Basic Salary + Meal Allowance + VB + Medical & Dental Benefits

Duration
Permanent Role

Key Responsibilities

• Develop layout designs based on schematic presentations.

• Implement layout designs, including the following:

• Floor planning and device placement.

• Power and signal routing, including signal and power integrity optimization.

• Perform DRC/LVS/ERC/ANT/ESD/PERC/LVL and other required physical verification checks.

• Ensure designs pass DRC requirements and meet LVS requirements.

• Prepare layout materials and conduct layout reviews.

• Follow checklists and methodologies to ensure layout quality.

• Improve and enhance layout methodologies.

• Participate in post-layout adjustments and block/IP-related activities.

• Apply a good understanding of AMS layout fundamentals, EMIR, RC delay, decoupling capacitors, and latch-up.

• Mentor and provide guidance to less experienced layout engineers.

• Participate in developing layout best practices and methodologies.

• Other ad-hoc duties as assigned.

Requirements

• Diploma or Bachelor's Degree in Electrical Engineering, Computer Engineering, Electronics Engineering, or an equivalent qualification.

• At least 6 years of hands-on experience in layout engineering.

• Experience with technology nodes below 16nm, high-speed or RF layout, and leading CAD tools, methodologies, and FinFET technology.

• Experience with Cadence SKILL or equivalent tools for PCell development, including Perl, Python, or TCL, and automation to improve layout productivity.

• Good understanding of process technology, circuit design, and CAD setup for analog layout physical verification.

• Experience with TX/RX/PLL/ADC/DAC and analog/digital chip-top integration is an advantage.

• Experience providing layout guidance to team members and ensuring layout quality.