Jobs in Bristol, Canada

Job Title: Senior Digital Design Engineer

Position: Full time permanent position

Location: Bristol

Salary Range: 50K – 80K GBP per annum depending on experience

Client Information:

My client is looking to strengthen their ASIC Digital Design team. They seek bright candidates with enthusiasm and aptitude for working with ASIC chips.

Designing chips for customers ranging from start-ups to blue chip companies across industries including automotive, medical, space, and mobile technology.

You should have a strong academic record, approximately 7-10 years of industry experience in ASIC development and IP design. Experience as a Technical Lead on at least one successful project could qualify you for a more senior role.

You will possess a broad understanding of the IC design flow, strong hands-on technical skills, excellent communication skills, and a desire to work in a customer-facing environment.

1. Take full ownership of all stages of the digital specification to RTL design flow for complex ASIC blocks or full-chip.
2. Collaborate closely with customers and team members to deliver projects on time and to quality standards.
3. Set up, run, and maintain EDA tool flows for each stage of the front-end design process.
4. Stay updated with advanced ASIC front-end design methodologies and best practices.

1. A 1st or 2.1 degree in Electronics, Physics, or a relevant subject from a Tier 1 university.
2. Approximately 7-10 years of IC development experience with comprehensive knowledge of ASIC front-end design, from specification to RTL, and a basic understanding of RTL to tape-out flow.
3. ASIC implementation skills including synthesis, DFT, and timing closure.
4. Experience leading complex IP or full ASIC designs from specification to RTL.
5. Technical expertise in:
1. RTL Design (VHDL or Verilog)
2. Functional verification, ideally with knowledge of SystemVerilog, assertions, and coverage-driven verification.
3. SoC knowledge, including selection and integration of third-party IPs.
4. Understanding of SoC interconnect protocols such as Amba AHB and AXI variants.