System-On-Chip Engineer

Intuition IT Solutions Ltd; Cambridge; On-site; GBP 101,000 - 166,000; Full time

Job summary

Intuition IT Solutions Ltd in Cambridge/Bristol UK is seeking a Senior SoC Design Verification Engineer to verify next-generation multi-die SoC designs. The role emphasizes System Verilog/UVM-based verification, regression execution, and processor-driven verification using Embedded C tests on cores.

You'll debug RTL, enhance existing verification environments, and drive coverage closure. Strong ARM-based SoC knowledge and scripting skills are required for efficient verification workflows within

Qualifications

• Strong hands-on experience in digital design verification using System Verilog and UVM.
• Experience modifying, extending, and debugging existing UVM testbenches.

Responsibilities

• Subsystem and SoC Functional Verification.
• Reuse and enhancement of System Verilog/UVM testbenches.
• Development and verification of processor-based C tests.
• Execute regressions, debug failures, and close coverage.
• Collaborate on verification planning with design teams.

Skills

SystemVerilog

UVM

Constrained-random verification

SoC architecture

Embedded C tests

RTL debugging

Python/Scripting

Regression management

Waveform debugging

Version control (Git)

Education

Bachelors or Masters in Electronics / Electrical / Computer Engineering / VLSI

Tools

Synopsys VCS

Cadence simulators

Waveform viewers

Embedded toolchains

Job description

Job Title - Senior SoC Design Verification Engineer
Location: Cambridge/Bristol UK,
Employment Type: Contract (Inside Ir35).

Role Overview

We are looking for experienced SoC Design Verification (DV) Engineers to work on the verification of a next-generation, multi-die System-on-Chip (SoC) design.
Engineers will be responsible for subsystem-level and SoC-level functional verification using System Verilog/UVM methodology, as well as processor-driven verification using C-based test programs executing on Embedded processor cores.

The role requires strong debugging and analytical skills, an understanding of ARM processor based SoC architecture, and the ability to efficiently adapt existing verification environments to evolving design requirements.

Key Responsibilities

• 1. Subsystem and SoC Functional Verification
• 2. System Verilog/UVM Testbench Reuse and Enhancement
• 3. Processor-Based C Test Development and Verification
• 4. Regression Execution, Debugging, and Coverage Closure
• 5. Verification Planning and Collaboration

Required Technical Skills

Essential Skills

• Strong hands-on experience in digital design verification using System Verilog and UVM.
• Experience working with existing UVM testbenches, including modifying, extending, and debugging reusable verification components.
• Good understanding of constrained-random verification, functional coverage, assertions, scoreboards, and checkers.
• Experience in subsystem-level or SoC-level functional verification.
• Strong understanding of SoC architectures, bus protocols, register interfaces, and processor-controlled peripherals.
• Experience developing, executing, or debugging Embedded C tests for processor-based SoC verification.
• Ability to debug complex RTL simulation failures using industry-standard simulators and waveform debugging tools.
• Experience executing regressions, analysing failures, and driving functional coverage closure.
• Working knowledge of Scripting languages such as Python, Perl, or Shell Scripting.
• Familiarity with version control systems and verification development workflows.

Candidate Profile

The ideal candidate should:

• Have strong practical experience in debugging and enhancing existing verification environments.
• Be comfortable understanding complex, previously developed UVM testbenches rather than relying exclusively on developing new environments from scratch.
• Demonstrate the ability to analyze design changes and identify required verification updates.
• Possess strong RTL debugging and problem-solving capabilities.
• Have experience working with large SoC verification regressions.
• Be capable of independently owning verification activities for assigned subsystems.
• Understand the relationship between UVM-based verification and processor-driven C test verification.

Educational Qualifications

Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, VLSI, or a related discipline.