Staff ASIC/RTL Digital Design Engineer — Lead

Technify Talent; Cambridgeshire and Peterborough; On-site; GBP 65,000 - 90,000; Full time

Job summary

Staff Digital Design Engineer – ASIC/RTL is a leadership role in an established semiconductor company in Cambridgeshire. You will drive digital development across architecture, RTL, verification, synthesis and physical implementation, collaborating with cross-functional teams to deliver high-quality mixed-signal ASICs from concept to production.

You’ll mentor engineers, contribute to design reviews, optimize PPA, implement DFT strategies and maintain thorough technical documentation to support

Qualifications

• Master's degree or higher in Electronics Engineering or related field.
• Minimum five years of digital IC design experience using standard-cell libraries.
• Strong SystemVerilog and RTL design skills with understanding of ASIC flows and EDA tools.
• Experience with synthesis, timing constraints, place-and-route and timing closure.
• Knowledge of DFT methodologies including scan architectures and ATPG.
• Experience optimizing digital designs for power, performance and area.
• Understanding of mixed-signal integration and lab debugging with test equipment.
• Proficiency in TCL and/or Python scripting.
• Strong documentation, problem-solving and cross-functional communication skills.
• Ability to provide technical leadership and drive continuous improvement.

Responsibilities

• Develop and review synthesisable SystemVerilog RTL for mixed-signal ASICs, from specification through to production.
• Support product definition, feasibility studies, architectural decisions and FPGA-based emulation.
• Develop testbenches, behavioural models and regression environments for functional verification.
• Execute digital synthesis and optimise designs for power, performance and area (PPA).
• Define and implement design-for-test (DFT) strategies including scan and ATPG.
• Oversee physical implementation, place-and-route and post-layout timing closure.
• Collaborate with analogue, product definition and test engineering teams for system integration.
• Produce technical documentation, contribute to design reviews and improve design flows.
• Provide technical guidance and leadership to other engineers.

Skills

SystemVerilog

RTL design

Leadership

Cross-functional collaboration

Scripting (TCL/Python)

Education

MSc/MEng/PhD in Electronics Engineering or related

Tools

Synopsys

Cadence

Mentor Graphics

Job description

Staff Digital Design Engineer – ASIC/RTL is a leadership role in an established semiconductor company in Cambridgeshire. You will drive digital development across architecture, RTL, verification, synthesis and physical implementation, collaborating with cross-functional teams to deliver high-quality mixed-signal ASICs from concept to production.

You’ll mentor engineers, contribute to design reviews, optimize PPA, implement DFT strategies and maintain thorough technical documentation to support