Software Verification Engineer

European Tech Recruit; Cambridge; On-site; GBP 50,000 - 75,000; Full time

Job summary

A global semiconductor giant is seeking a Formal Verification Engineer to join their Cambridge team. The role involves developing formal verification strategies, collaborating with various teams to meet project goals, and debugging RTL artifacts. Ideal candidates will have experience with formal verification tools, proficiency in SystemVerilog Assertions, and strong communication skills. On-site work is required, and this is an excellent opportunity to contribute to innovative verification methodologies.

Qualifications

• Hands-on experience with formal verification tools.
• Proficiency in SystemVerilog Assertions.
• Strong experience in achieving formal verification sign-off.

Responsibilities

• Develop a deep understanding of the 3D graphics hardware pipeline.
• Plan and implement Formal Property Verification strategies.
• Collaborate globally with GPU architecture and DV teams.

Skills

Formal verification tools and techniques

SystemVerilog Assertions

Bug-hunting

Communication skills

Quick learner

Job description

A Global semiconductor giant based in Cambridge are seeking to bolster their team with a talented Formal Verification Engineer.

Please note this opportunity is based on-site in Cambridge.

Responsibilities:

• Develop a deep understanding of the 3D graphics hardware pipeline, including feature sets, data paths, block functionalities, and interfaces
• Plan and implement Formal Property Verification (FPV) strategies, including assertion-based testbenches, formal proofs, and sign-off matrices
• Collaborate with GPU architecture, RTL design, and DV teams globally to ensure project goals and quality targets are met
• Debug RTL artifacts, drive coverage closure, and resolve complex verification challenges in formal proof environments
• Engage with EDA vendors and explore innovative formal verification methodologies to enhance verification quality and efficiency

Requirements:

• Hands-on experience with industry-standard formal verification tools and techniques
• Proficiency in writing SystemVerilog Assertions and managing formal proof complexity using abstraction methods
• Strong experience in bug-hunting, coverage closure, and achieving formal verification sign-off
• Knowledge of GPU architecture is advantageous but not required; familiarity with additional formal applications such as DPV, C-to-RTL SEQ, or RTL-to-RTL SEQ is a plus
• Excellent communication skills, ability to learn quickly, and a proactive approach to delivering high-quality results

If this role is of interest please apply directly on LinkedIn or send a copy of your CV to [e-mail].

By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice (https://eu-recruit.com/about-us/privacy-notice/)