A global semiconductor giant is seeking a Formal Verification Engineer to join their Cambridge team. The role involves developing formal verification strategies, collaborating with various teams to meet project goals, and debugging RTL artifacts. Ideal candidates will have experience with formal verification tools, proficiency in SystemVerilog Assertions, and strong communication skills. On-site work is required, and this is an excellent opportunity to contribute to innovative verification methodologies.
Qualifications
Hands-on experience with formal verification tools.
Proficiency in SystemVerilog Assertions.
Strong experience in achieving formal verification sign-off.
Responsibilities
Develop a deep understanding of the 3D graphics hardware pipeline.
Plan and implement Formal Property Verification strategies.
Collaborate globally with GPU architecture and DV teams.
Skills
Formal verification tools and techniques
SystemVerilog Assertions
Bug-hunting
Communication skills
Quick learner
Job description
A global semiconductor giant is seeking a Formal Verification Engineer to join their Cambridge team. The role involves developing formal verification strategies, collaborating with various teams to meet project goals, and debugging RTL artifacts. Ideal candidates will have experience with formal verification tools, proficiency in SystemVerilog Assertions, and strong communication skills. On-site work is required, and this is an excellent opportunity to contribute to innovative verification methodologies.