Senior Verification Engineer: RTL/UVM for 4G/5G Modems

Spectrum IT Recruitment; England; On-site; GBP 65,000 - 80,000; Full time

Job summary

Spectrum IT Recruitment is seeking a Senior Verification Engineer to join an RTL team delivering advanced communications tech for ASIC and FPGA platforms. You will own UVM verification of complex wireless IP and modem subsystems, ensuring designs meet functional and performance targets ahead of FPGA deployment and ASIC tape-out.

You will mentor junior engineers and collaborate across multiple teams on challenging IP development, integration and verification efforts with a strong focus on

Qualifications

• Degree in Electronic or Computer Engineering.
• 3+ years of experience verifying digital ASIC/FPGA designs.
• Strong SystemVerilog and UVM experience.
• Knowledge of RTL design principles.
• Experience with coverage-driven and assertion-based verification.
• Linux proficiency with Python, Tcl or Bash scripting.
• Analytical, debugging, and problem-solving skills.
• Experience using AI to accelerate verification while maintaining quality.
• Ability to collaborate across multiple engineering teams.

Responsibilities

• Develop verification plans from design and architecture specs.
• Create and maintain SystemVerilog/UVM verification environments.
• Develop testbenches, assertions, scoreboards and coverage models.
• Carry out directed and constrained-random verification.
• Analyse coverage and debug RTL and verification issues.
• Support subsystem and system-level integration.
• Contribute to automation, regression testing and CI workflows.
• Participate in design reviews and verification sign-off.
• Mentor and support junior engineers.

Skills

SystemVerilog

UVM

RTL design

Coverage-driven verification

Assertion-based verification

Linux scripting (Python/Tcl/Bash)

Debugging

AI-assisted verification

Cross-team collaboration

Education

Electronic/Computer Engineering degree

Tools

MATLAB

Job description

Spectrum IT Recruitment is seeking a Senior Verification Engineer to join an RTL team delivering advanced communications tech for ASIC and FPGA platforms. You will own UVM verification of complex wireless IP and modem subsystems, ensuring designs meet functional and performance targets ahead of FPGA deployment and ASIC tape-out.

You will mentor junior engineers and collaborate across multiple teams on challenging IP development, integration and verification efforts with a strong focus on