Senior Verification Engineer, Media IP & DPU

CamWebDir; United Kingdom; Hybrid; GBP 70,000 - 95,000; Full time

Job summary

Arm is seeking an experienced verification engineer to lead the verification of a DPU subsystem within the Systems Media IP team. You will architect high-performance SystemVerilog/UVM environments and ensure robust verification across multiple units, aligning with project plans and schedules.

You will work with Python/C for tooling and contribute to verification strategies, tests, coverage, and integration into complete systems.

Qualifications

• Extensive hands-on SystemVerilog and UVM verification experience.
• Experience with on-chip buses (AMBA AXI, APB) protocols.

Responsibilities

• Own and drive verification for a DPU subsystem with multiple units from planning to sign-off.
• Architect reusable, scalable SystemVerilog/UVM environments and verification IP.
• Define verification plans, coverage models, sign-off criteria and quality goals.
• Lead resolution of complex unit-, cross-unit-, or system-level failures.
• Collaborate with architecture, design, software and Arm teams to ensure successful integration.

Skills

SystemVerilog

UVM

AMBA AXI

Python

C

Verification architecture

Tools

Git

CI/CD

Job description

Arm is seeking an experienced verification engineer to lead the verification of a DPU subsystem within the Systems Media IP team. You will architect high-performance SystemVerilog/UVM environments and ensure robust verification across multiple units, aligning with project plans and schedules.

You will work with Python/C for tooling and contribute to verification strategies, tests, coverage, and integration into complete systems.