Senior Verification Engineer

TN United Kingdom; Cambridge; Hybrid; GBP 50,000 - 90,000; Full time

Job summary

An innovative company is seeking a Senior Verification Engineer to join their talented team in Cambridge. In this role, you will lead verification efforts, ensuring the reliability and performance of cutting-edge solutions in quantum computing. Collaborate with hardware designers and embedded software engineers to define and implement comprehensive verification strategies. This position offers the opportunity to work on groundbreaking technology while enjoying a hybrid work environment, competitive benefits, and a commitment to personal and professional growth. Join a diverse team and contribute to a mission that aims to solve some of the world's most pressing challenges.

Benefits

Annual Bonus Scheme

Private Medical Insurance

Life Insurance

Contributory Pension Scheme

28 Days Annual Leave

Enhanced Family Leave

Training and Conference Budget

Equity Options

Qualifications

• Demonstrable experience in functional verification and planning.
• Proven experience in testbench design with frameworks like UVM/OVM.

Responsibilities

• Define verification plans based on design specifications.
• Implement scalable testbenches in SystemVerilog.

Skills

Functional Verification

Verification Planning

Testbench Design

SystemVerilog

C

C++

Python

Formal Verification

Tools

UVM

OVM

Job description

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Cambridge, UK | Full-time or Part-time | Permanent | Hybrid

We will also consider part-time applications for this role. Please indicate your preferred working schedule in your cover letter.

About us

Riverlane’s mission is to make quantum computing useful, sooner. From advances in material science to complex chemistry simulation for drug design and discovery, quantum computers will help solve some of the world’s most important challenges. Riverlane is building the quantum error correction stack, Deltaflow, to make this happen. It’s a complex problem that requires a range of skills, talent and passion.

We recently raised $75M in Series C funding to accelerate our cutting-edge R&D in quantum error correction (QEC), and are partnering with many of the world’s leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality. We’re making remarkable progress and growing fast.

About the role

You will work with our talented team of hardware designers and embedded software engineers to produce a fully verified, trusted and performant solution. With full visibility of the entire stack, you will own everything verification related. As a Senior Verification Engineer at Riverlane, you will:

• Proactively work with designers and architects to define verification plans based on design specifications. You will own, define and track detailed test plans for different blocks and system level.
• Implement scalable testbenches, including checkers, reference models and coverage groups in SystemVerilog. You will implement self-testing, directed and random tests.
• Maintain the design verification environment, keeping track of regression, coverage metrics and bugs.

You do not need a background in quantum computing! You will learn this along the way...

What you will do

You will work with our talented team of hardware designers and embedded software engineers to produce a fully verified, trusted and performant solution. With full visibility of the entire stack, you will own everything verification related. As a Senior Verification Engineer at Riverlane, you will:

• Proactively work with designers and architects to define verification plans based on design specifications. You will own, define and track detailed test plans for different blocks and system level.
• Implement scalable testbenches, including checkers, reference models and coverage groups in SystemVerilog. You will implement self-testing, directed and random tests.
• Maintain the design verification environment, keeping track of regression, coverage metrics and bugs.

You do not need a background in quantum computing! You will learn this along the way...

Requirements

What we need

• Demonstrable commercial experience in functional verification, including ownership of verification planning and strategy.
• A proactive and collaborative person who actively shares feedback and who can independently define the scope of work.
• Proven experience of testbench design with verification frameworks like UVM/OVM.
• Knowledge of SystemVerilog assertion (SVA).
• Exposure to different programming languages, such as C, C++ and Python
• You have formal verification experience

What you can expect from us

• A comprehensive benefits package, including annual bonus scheme, private medical insurance, life insurance, a contributory pension scheme (and much more)
• Equity so that our team can share in the long-term success of Riverlane
• 28 days annual leave (plus bank holidays) and enhanced family leave
• A diverse work environment that brings together experts in many fields (including software and hardware development, quantum information theory, physics, maths and many more) and over 20 different nationalities
• A learning environment that encourages individual, team and company growth and learning, including an annual training and conference budget

How to apply

Please upload a CV and cover letter by clicking 'Apply'. Your cover letter should explain why you are applying for the job and what skills and experience you can bring to the role.

We review CVs as we receive them and interview as soon as we have applications that look like a good match (usually within one week). We do not use closing dates. So, please apply as soon as possible to avoid missing out on this role. We advertised this role on 4th April 2025. If you have any queries, please contact[emailprotected] .

Everyone is welcome at Riverlane. We are an equal opportunities employer and encourage applications from eligible and suitably qualified candidates regardless of age, disability, ethnicity, gender, gender reassignment, religion or belief, sexual orientation, marital or civil partnership status, or pregnancy and maternity/paternity.

Studies have shown that women tend to apply to jobs if they meet all or almost all of the requirements whereas men apply even if they meet only some of the requirements. If that sounds like you then please apply – we are happy to review your application and let you know if we think you might be a good fit.

If you need any adjustments made to the application or selection process so you can do your best, please let us know. We will be happy to help.