Senior Verification Engineer

Riverlane; Cambridge; Hybrid; GBP 65,000 - 80,000; Full time

Job summary

This innovative firm is seeking a Senior Verification Engineer to join their talented team in quantum computing. You will play a crucial role in defining and implementing verification plans, ensuring the performance and reliability of cutting-edge technology. With a focus on collaboration and proactive problem-solving, you will work on complex challenges that push the boundaries of quantum error correction. The company fosters a diverse and inclusive work environment, offering opportunities for growth and learning. If you're passionate about technology and eager to make an impact, this role is perfect for you.

Benefits

Annual Bonus Scheme

Private Medical Insurance

Life Insurance

Contributory Pension Scheme

28 Days Annual Leave

Enhanced Family Leave

Annual Training Budget

Diverse Work Environment

Equity Participation

Qualifications

• Commercial experience in functional verification with planning ownership.
• Proven testbench design experience with verification frameworks.

Responsibilities

• Define verification plans based on design specifications.
• Implement scalable testbenches and maintain the verification environment.

Skills

Functional Verification

Verification Planning

Testbench Design

SystemVerilog

C Programming

C++ Programming

Python Programming

Tools

UVM

OVM

Job description

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Location: Cambridge, UK

Employment Type: Full-time or Part-time Permanent Hybrid

Salary: £65,000 to £80,000 DOE

We will also consider part-time applications for this role. Please indicate your preferred working schedule in your cover letter.

About us

Riverlane's mission is to make quantum computing useful, sooner. From advances in material science to complex chemistry simulation for drug design and discovery, quantum computers will help solve some of the world's most important challenges. Riverlane is building the quantum error correction stack, Deltaflow, to make this happen. It's a complex problem that requires a range of skills, talent and passion.

We recently raised $75M in Series C funding to accelerate our cutting-edge R&D in quantum error correction (QEC), and are partnering with many of the world's leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality. We're making remarkable progress and growing fast.

About the role

You will work with our talented team of hardware designers and embedded software engineers to produce a fully verified, trusted and performant solution. With full visibility of the entire stack, you will own everything verification related. As a Senior Verification Engineer at Riverlane, you will:

1. Proactively work with designers and architects to define verification plans based on design specifications. You will own, define and track detailed test plans for different blocks and system level.
2. Implement scalable testbenches, including checkers, reference models and coverage groups in SystemVerilog. You will implement self-testing, directed and random tests.
3. Maintain the design verification environment, keeping track of regression, coverage metrics and bugs.

You do not need a background in quantum computing! You will learn this along the way...

Requirements

What we need

1. Demonstrable commercial experience in functional verification, including ownership of verification planning and strategy.
2. A proactive and collaborative person who actively shares feedback and who can independently define the scope of work.
3. Proven experience of testbench design with verification frameworks like UVM/OVM.
4. Knowledge of SystemVerilog assertion (SVA).
5. Exposure to different programming languages, such as C, C++ and Python.

Even better if

1. You have formal verification experience.

Benefits

What you can expect from us

1. A comprehensive benefits package, including annual bonus scheme, private medical insurance, life insurance, a contributory pension scheme (and much more).
2. Equity so that our team can share in the long-term success of Riverlane.
3. 28 days annual leave (plus bank holidays) and enhanced family leave.
4. A diverse work environment that brings together experts in many fields (including software and hardware development, quantum information theory, physics, maths and many more) and over 20 different nationalities.
5. A learning environment that encourages individual, team and company growth and learning, including an annual training and conference budget.

How to apply

Please upload a CV and cover letter by clicking 'Apply'. Your cover letter should explain why you are applying for the job and what skills and experience you can bring to the role.

We review CVs as we receive them and interview as soon as we have applications that look like a good match (usually within one week). We do not use closing dates. So, please apply as soon as possible to avoid missing out on this role. We advertised this role on 4th April 2025. If you have any queries, please contact [e-mail].

Everyone is welcome at Riverlane. We are an equal opportunities employer and encourage applications from eligible and suitably qualified candidates regardless of age, disability, ethnicity, gender, gender reassignment, religion or belief, sexual orientation, marital or civil partnership status, or pregnancy and maternity/paternity.

Studies have shown that women tend to apply to jobs if they meet all or almost all of the requirements whereas men apply even if they meet only some of the requirements. If that sounds like you then please apply - we are happy to review your application and let you know if we think you might be a good fit.

If you need any adjustments made to the application or selection process so you can do your best, please let us know. We will be happy to help.