Senior Quantum Chip Architect for QPU Systems

NightDragon Acquisition Corp.

Oxford

Hybrid

GBP 110,000 - 170,000

Full time

3 days ago
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Benefits offered by this job

comprehensive medical, dental, and ves
matching 401(k)
unlimited PTO and paid holidays
parental/adoption leave
legal insurance
home technology stipend

Job summary

IonQ, Oxford Ionics, is seeking a Senior QPU Design Engineer to join the Processor Design team in Oxford. You will help translate requirements into chip layouts and collaborate with scientists and fabrication engineers to advance ion‑trapping hardware.

You will guide chips through the full design process, lay out multi‑layer chips with metal routing and photonics interfaces, and own the delivery of the final tape‑out. Strong layout experience and cross‑team collaboration are essential.

Qualifications

  • Experience translating design requirements into features.
  • Hands-on chip layout experience.
  • Ability to work across teams and discuss chip design.
  • Willingness to take charge of projects independently.

Responsibilities

  • Guiding chips through the design process, from requirements to layout and tape out.
  • Laying out complex multi layer chips, including metal track routing and interfaces with photonics and CMOS.
  • Collaborating with scientists to discuss their requirements and settle on specifications.
  • Coordinating with other teams to ensure feasibility and compatibility.
  • Taking charge of projects independently and owning delivery of the final tape out.

Skills

Chip layout
Cross-team collaboration
Project ownership
Design process leadership

Tools

Cadence IC layout
GDSFactory (Python)
Ion trap design

Job description

IonQ, Oxford Ionics, is seeking a Senior QPU Design Engineer to join the Processor Design team in Oxford. You will help translate requirements into chip layouts and collaborate with scientists and fabrication engineers to advance ion‑trapping hardware.

You will guide chips through the full design process, lay out multi‑layer chips with metal routing and photonics interfaces, and own the delivery of the final tape‑out. Strong layout experience and cross‑team collaboration are essential.

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