Our client is looking for a highly experienced Senior Principal CPU Architect to help define the next generations of high-performance CPU architecture.
This is a strategic individual-contributor position focused on long-term CPU architecture, ISA development, advanced microarchitecture, workload analysis and hardware/software co-design.
You will help shape CPU technologies several years ahead of production and work on computational challenges including Generative AI, LLMs, graph analytics and confidential computing.
Key Responsibilities
- Lead architectural pathfinding for next-generation CPU designs and technologies.
- Define microarchitectural concepts covering fetch/decode, execution pipelines, out-of-order scheduling and multi-level memory hierarchies.
- Evaluate and define new ISA capabilities, including vector/matrix extensions and specialised compute instructions.
- Analyse emerging workloads and translate software bottlenecks into microarchitectural requirements.
- Work closely with compiler, operating system and application software teams on hardware/software co-design.
- Guide development of C++ and Python based cycle-accurate CPU simulation models.
- Evaluate architectural concepts across performance, power and area.
- Provide senior technical leadership and contribute to longer-term technology roadmaps.
Requirements
- Extensive industry experience in high-performance CPU architecture.
- Deep understanding of out-of-order execution, branch prediction, register renaming, speculative execution, cache hierarchies and coherency protocols.
- Strong understanding of ISA design, exception models, memory consistency and virtualisation.
- Experience with workload profiling, performance counters and simulation traces.
- Familiarity with tools such as VTune, Perf, SimPoints or similar performance analysis environments.
- Strong experience developing cycle-accurate architectural simulators using C, C++ and Python.
- MS or PhD in Computer Engineering, Computer Science, Electrical Engineering or a related discipline.
- Experience delivering multiple high-performance CPU designs through silicon tape-out.
- Experience with x86, Arm and/or RISC-V.
- Contributions to LLVM, GCC, architectural frameworks or open ISA communities.
- Knowledge of chiplets, 3D stacking and advanced semiconductor packaging.