A leading technology recruitment firm in the United Kingdom is seeking a Senior Architect to work on the latest CPU architecture developments. The role involves performance analysis, optimization, and implementation of new instructions in performance simulators. Ideal candidates will have deep understanding of CPU architectures, experience with Aarch64 or X86 instruction sets, and strong collaboration skills. This position offers the chance to significantly impact processing power and performance improvements.
Qualifications
Experience with performance simulators like GEM5 or Sniper is a plus.
Knowledge of NPU/GPU architecture is valued.
Experience in ARM/x86 instruction implementation preferred.
Responsibilities
Analyze performance of applications for new instructions.
Optimize critical application parts to support new ISA.
Implement new instructions in performance simulator.
Skills
Deep understanding of modern CPU architectures
Knowledge of latest Aarch64 or X86 instruction sets
Background in performance analysis
Excellent collaboration and interpersonal skills
Tools
GEM5
QEMU
DynamoRIO
Job description
This is a key position as a senior architect – to work on the latest developments in CPU architecture – for improvements in processing power, performance and optimisation.
Main Responsibilities
Performance analysis of applications of interest to propose new instructions and ISA extensions.
Reworking and optimisation of critical parts of applications to support new ISA.
Implementation of proposed new instructions or uArch tweaks in performance simulator for evaluation of possible performance benefits.
Requirement
Deep understanding of modern CPU architectures
Knowledge and experience of using of latest Aarch64 or X86 instruction sets.
Background in performance analysis, profiling and workload characterization.
Excellent collaboration and interpersonal skills
Considered as a plus
Experience in developing and using performance simulators like GEM5 (O3 model), Sniper or others is a big plus.
Experience in developing and using dynamic binary instrumentation infrastructures like QEMU or DynamoRIO or x86 PIN is a plus.
Knowledge of NPU/GPU architecture
Experience in simulator development for NPU/GPU
Experience in implementing instructions in the ARM/x86 architecture is preferred.